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179 lines
6.6 KiB
179 lines
6.6 KiB
#!/usr/bin/env python3
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# This file is Copyright (c) 2020 Wolfgang Villing <ringel@it-ringel.de>
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# SPDX-License-Identifier: BSD-3-Clause
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import math
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from migen import *
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from migen.fhdl import verilog
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from litex.soc.interconnect.csr import *
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class ColorDim(Module):
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"""Binary dimming for RGB332 Colors"""
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def __init__(self):
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self.pixUpper = Signal(8)
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self.pixLower = Signal(8)
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self.output = Signal(6)
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self.resetCounter = Signal()
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self.incrementCounter = Signal()
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self.oen = Signal()
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self.done = Signal()
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self.active = Signal()
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self.waitForLast = Signal()
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pulseduration = Signal(22)
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bitToCheck = Signal(3)
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self.sync += If( self.resetCounter,
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pulseduration.eq(0),
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bitToCheck.eq(0b100)
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).Elif(self.incrementCounter,
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pulseduration.eq(bitToCheck << 5), # Multiply by 16 for Max Brightness
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bitToCheck.eq(bitToCheck >> 1)
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).Else(
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If((pulseduration == 0),
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pulseduration.eq(0)
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).Else(
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pulseduration.eq(pulseduration - 1)
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)
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)
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self.comb += self.active.eq(pulseduration != 0)
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self.comb += self.oen.eq(pulseduration == 0)
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self.comb += self.done.eq((bitToCheck == 0) & (pulseduration == 0))
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self.comb += self.waitForLast.eq((bitToCheck == 0) & (pulseduration != 0))
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r1, r2, g1, g2, b1, b2 = [Signal() for _ in range(6)]
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self.comb += r1.eq(self.pixUpper[5:8] & bitToCheck > 0)
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self.comb += r2.eq(self.pixLower[5:8] & bitToCheck > 0)
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self.comb += g1.eq(self.pixUpper[2:5] & bitToCheck > 0)
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self.comb += g2.eq(self.pixLower[2:5] & bitToCheck > 0)
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self.comb += b1.eq(self.pixUpper[0:2] & bitToCheck[1:3] > 0)
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self.comb += b2.eq(self.pixLower[0:2] & bitToCheck[1:3] > 0)
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self.comb += self.output.eq(Cat(r1, g1, b1, r2, g2, b2))
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class Hub75Out(Module):
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def __init__(self):
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self.rgb = Signal(6)
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self.adr = Signal(5)
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self.clk = Signal()
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self.lat = Signal()
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self.oen = Signal()
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class Hub75Sender(Module, AutoCSR):
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"""Hub75 LED Matrix driver. Framebuffer Colorformat RGB332"""
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def __init__(self, numCols=8, numRows=4, content=None, out=None):
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addressOffset = Constant(numCols * numRows/2)
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rowCountShift = math.ceil(math.log2(numCols))
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memSize = numCols * numRows
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#self.status = CSRStatus(32)
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# Memory mapped to Wishbone - having second read port
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self.specials.mem = Memory(8, memSize, init=content)
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ram = self.mem.get_port()
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self.specials += ram
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pwm = ColorDim()
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self.submodules += pwm
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# Pixel and Row counter
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self.pixCount = Signal(max=numCols+1)
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self.rowCount = Signal(max=numRows)
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# Output Ports
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self.outAddr = Signal(5) # abcde
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self.outClk = Signal()
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self.outLat = Signal()
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self.outRGB = Signal(6) # (6) r0 r1 g0 g1 b0 b1
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self.comb += self.outRGB.eq(pwm.output),
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self.frameDone = Signal() # Debug
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self.rowDone = Signal() # Debug
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if out:
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self.comb += out.rgb.eq(self.outRGB)
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self.comb += out.adr.eq(self.outAddr)
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self.comb += out.lat.eq(self.outLat)
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self.comb += out.clk.eq(self.outClk)
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self.comb += out.oen.eq(pwm.oen)
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fsm = FSM(reset_state="RESET")
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self.submodules.fsm = fsm
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fsm.act("RESET",
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NextValue(self.pixCount, 0),
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NextValue(self.rowCount, 0),
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pwm.resetCounter.eq(1),
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NextState("AdrUp"))
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fsm.act("AdrUp", # Address upper Pixel
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ram.adr.eq(self.pixCount + (self.rowCount << rowCountShift)),
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NextState("AdrLo"))
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fsm.act("AdrLo", # Address lower Pixel + Readout Upper Pixel data
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ram.adr.eq((self.pixCount + addressOffset) + (self.rowCount << rowCountShift)),
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NextValue(self.pixCount, self.pixCount+1),
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NextValue(pwm.pixUpper, ram.dat_r),
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NextState("ReadLow"))
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fsm.act("ReadLow", # Readout Lower Pixel data
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NextValue(pwm.pixLower, ram.dat_r),
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NextState("ClkOn"))
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fsm.act("ClkOn", # Clock the Data out
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NextValue(self.outClk, 1),
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NextState("ClkOff"))
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fsm.act("ClkOff", # Clock the Data out
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NextValue(self.outClk, 0),
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If(pwm.active & (self.pixCount == numCols),
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NextState("ClkOff") # Wait for last Dimming done
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).Elif(self.pixCount == numCols,
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NextValue(self.pixCount, 0),
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NextState("RowOk") # Finished with Row
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).Else(
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# Skip AddrUp State and set Address here
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ram.adr.eq(self.pixCount + (self.rowCount << rowCountShift)),
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NextState("AdrLo")
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))
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fsm.act("RowOk", NextValue(self.outLat, 1), NextState("LatOn"))
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fsm.act("LatOn", NextState("AdrRow"))
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fsm.act("AdrRow", NextValue(self.outLat, 0), NextState("LatOff"))
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fsm.act("LatOff", pwm.incrementCounter.eq(1), NextState("CkCnt"))
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fsm.act("CkCnt",
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If(pwm.waitForLast,
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NextState("CkCnt")
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).Elif(pwm.done,
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If(self.rowCount == Constant(numRows/2 - 1),
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NextValue(self.rowCount, 0),
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self.frameDone.eq(1)
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).Else(
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NextValue(self.rowCount, self.rowCount + 1),
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),
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NextState("OeOn"),
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pwm.resetCounter.eq(1)
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).Else(
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NextState("AdrUp")
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)
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)
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fsm.act("OeOn",
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NextValue(self.outAddr, self.rowCount),
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NextState("Done"))
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fsm.act("Done", self.rowDone.eq(1), NextState("AdrUp"))
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def testbench():
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content = (0, 1, 2, 3,
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0, 0, 0, 0,
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0x00, 0x04, 0x08, 0x0C, 0, 0, 0, 0)
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dut = Hub75Sender(4, 4, content, Hub75Out())
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def memtest():
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for _ in range(1000):
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yield
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yield
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#print(verilog.convert(dut, dut.ios))
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run_simulation(dut, memtest(), vcd_name="hub75sender.vcd", clocks={"sys": 1000})
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