Litex System on Colorlight Board. ECP5 FPGA runs Risc-V Core and custom Hardware
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
 

127 lines
4.7 KiB

#!/usr/bin/env python3
# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
import os
import argparse
from litex.soc.cores.clock import *
from litex.soc.cores.spi_flash import ECP5SPIFlash
from litex.soc.cores.gpio import GPIOOut, GPIOIn
from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.build.lattice.trellis import trellis_args, trellis_argdict
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
from litex.build.generic_platform import *
from litex_boards.targets import colorlight_5a_75x
from basic_system.hub75sender import Hub75Sender
from basic_system.bit_to_flash import convertBitToFlashFile
_gpios = [
("gpio", 0, Pins("j4:1"), IOStandard("LVCMOS33")),
("gpio", 1, Pins("j4:5"), IOStandard("LVCMOS33")),
("j5", 0, Pins("j5:0"), IOStandard("LVCMOS33")),
("j5", 1, Pins("j5:1"), IOStandard("LVCMOS33")),
("j5", 2, Pins("j5:2"), IOStandard("LVCMOS33")),
("j5", 3, Pins("j5:4"), IOStandard("LVCMOS33")),
("j5", 4, Pins("j5:5"), IOStandard("LVCMOS33")),
("j5", 5, Pins("j5:6"), IOStandard("LVCMOS33")),
("j5", 6, Pins("j5:7"), IOStandard("LVCMOS33")),
("j5", 7, Pins("j5:8"), IOStandard("LVCMOS33")),
]
ios = [
("led", 0, Pins("j4:1 j4:5"), IOStandard("LVCMOS33")),
("j5", 0,
Subsignal("rgb", Pins("j5:0 j5:1 j5:2 j5:4 j5:5 j5:6")),
Subsignal("adr", Pins("j5:8 j5:9 j5:10 j5:11 j5:7")),
Subsignal("clk", Pins("j5:12")),
Subsignal("lat", Pins("j5:13")),
Subsignal("oen", Pins("j5:14")),
IOStandard("LVCMOS33"))
]
def load(file):
import os
os.system("mkdir -p prog")
print("--------")
f = open("prog/openocd.cfg", "w")
f.write(
"""
interface vsllink
adapter_khz 100
reset_config none
jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
""")
f.close()
os.system(f"openocd -f prog/openocd.cfg -c \"transport select jtag; init; svf {file}; exit\"")
exit()
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75X")
builder_args(parser)
soc_core_args(parser)
trellis_args(parser)
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--flash", action="store_true", help="Load bitstream to flash")
parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator")
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
parser.set_defaults(uart_name='crossover', no_uart=False, cpu_type="vexriscv")
args = parser.parse_args()
soc = colorlight_5a_75x.BaseSoC(board="5a-75b", revision="7.0",
sys_clk_freq = 60e6,
use_internal_osc = args.use_internal_osc,
sdram_rate = args.sdram_rate,
**soc_core_argdict(args))
soc.platform.name ="clFull"
# 32MBit SPIFlash ---------------------------------------------------------------------------------
soc.mem_map["spiflash"] = 0xc0000000
# Boot at +1MB
soc.add_constant("FLASH_BOOT_ADDRESS", soc.mem_map["spiflash"] + 1024*1024)
soc.add_spi_flash(name="spiflash", mode="1x", dummy_cycles=8, clk_freq=5e6)
soc.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=soc.platform.request("eth_clocks", 0),
pads=soc.platform.request("eth", 0))
soc.add_csr("ethphy")
soc.add_etherbone(name="etherbone", phy=soc.ethphy,
mac_address=0x10e2d5000000,
ip_address="10.42.1.222",
udp_port=1234)
# GPIOs ------------------------------------------------------------------------------------
soc.platform.add_extension(ios)
# soc.submodules.led = GPIOOut(soc.platform.request("user_led_n"))
# soc.add_csr("led")
soc.submodules.hub = Hub75Sender(64, 64, (0xff, 0xe0, 0x1c, 0x03), soc.platform.request("j5"))
soc.add_csr("hub_mem")
soc.add_csr("hub")
counter = Signal(32)
soc.sync += counter.eq(counter + 1)
soc.comb += soc.platform.request("user_led_n").eq(counter[24])
builder = Builder(soc, output_dir="build", csr_csv="scripts/csr.csv")
builder.build(**trellis_argdict(args), run=args.build)
if args.flash: # Convert Bit File to Jtag Write Flash command
name = os.path.join(builder.gateware_dir, soc.build_name)
convertBitToFlashFile(name+".bit", name+".svf.flash")
load(name + ".svf.flash")
return
if args.load: # Temporary Load into FPGA
load(os.path.join(builder.gateware_dir, soc.build_name + ".svf"))
if __name__ == "__main__":
main()