224 lines
10 KiB
Python
224 lines
10 KiB
Python
#!/usr/bin/env python3
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#
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# bfloat16nncore.py
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#
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# bfloat16 neural network processing core logic
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#
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# History:
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# --------
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# 21.04.21/KQ Initial version
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#
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from migen import *
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from migen.fhdl.specials import Memory
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage, CSRField, CSRAccess
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from litex.soc.integration.doc import AutoDoc, ModuleDoc
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from litex.soc.interconnect.csr import *
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from libmodules.dramtransfer import DRAM2FPGA, FPGA2DRAM
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from libmodules.bfloat16processor import bfloat16Processor
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class bfloat16NeuralNetworkCore(Module, AutoCSR, AutoDoc, ModuleDoc):
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"""
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bfloat16NN core class:
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Usage:
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######
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1. Freeze operations by setting ``bEnable`` to false (0)
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2. Load ``b32DRAMAddress`` with a 32-bit DRAM memory pointer.
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3. Finally, enable processing by setting ``bEnable`` to true (1).
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4. bfloat16NN processing will now run async. to CPU until reset or s.a. (1.).
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CPU from now on will write to DRAM only (yet, L2 cache will have to be flushed),
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all data will be picked up by FPGA automatically ...
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Inputs:
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#######
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:b32DRAMAddress: New DRAM address from where to load into local memory
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:b32Sentinel: Write control word to last address (same as [b32DRAMAddress+511] value)
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:bEnable: To enable running (after data preparation)
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Outputs:
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########
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:b16Result: Processing result
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:bReady: Ready indication (wire to LED ... ;)
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"""
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def __init__(self, RAMWaitTime=128, LUCacheSize=8, LoadUnit=None, StoreUnit=None):
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# Inputs
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self.b32DRAMLoadAddress = CSRStorage(32, reset_less=False,
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fields=[CSRField("LoadAddress", size=32, description="*Field*: 32-Bit value")],
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description="""
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Load value (32-bit DRAM address).
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""")
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self.b32Sentinel = CSRStorage(32, reset_less=False,
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fields=[CSRField("Sentinel", size=32, description="*Field*: 32-Bit value")],
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description="""
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Control value
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""")
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self.bEnable = CSRStorage(1, reset_less=False,
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fields=[CSRField("Enable", size=1, description="*Field*: bit", values=[
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("0", "DISABLED", "bfloat16NN not active"),
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("1", "ENABLED", "bfloat16NN active"),
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])
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],
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description="""
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Enable free run
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""")
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# Outputs
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self.b16Status = CSRStorage(16, reset_less=False,
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fields=[CSRField("Status", size=16, description="*Field*: 16-Bit value")],
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description="""
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Processing stati
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""")
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self.b16Value1 = CSRStorage(16, reset_less=False,
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fields=[CSRField("Value", size=16, description="*Field*: 16-Bit value")],
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description="""
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Float register 1
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""")
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self.b16Value2 = CSRStorage(16, reset_less=False,
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fields=[CSRField("Value", size=16, description="*Field*: 16-Bit value")],
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description="""
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Float register 2
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""")
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self.b16Value3 = CSRStorage(16, reset_less=False,
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fields=[CSRField("Value", size=16, description="*Field*: 16-Bit value")],
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description="""
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Float register 3
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""")
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self.b16Result = CSRStorage(16, reset_less=False,
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fields=[CSRField("Result", size=16, description="*Field*: 16-Bit value")],
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description="""
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Processing result
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""")
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self.bReady = Signal() # To be wired to data pin ... ;)
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# Local vars.
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# - none yet -
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#---------------- Load unit (LU) -------------------------------------------------------------
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LU_fsm = FSM(reset_state="LU_IDLE") # FSM starts idling ...
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self.submodules += LU_fsm
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self.LU_CacheOffset = Signal(9, reset_less=True) # 0..511 log2_int(LUCacheSize, False)) # Cache reading offset (0..(Size-1))=>Bits)
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self.LU_CacheValid = Signal() # Indicate loaded LU cache
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self.LU_CacheDelay = Signal(11, reset_less=True) # Evaluate load length in cycles (2048 max.)
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LU_fsm.act("LU_IDLE", # If cache not valid fill it!
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If(~self.LU_CacheValid & self.bEnable.storage, # Invalid cache & run enabled ...
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NextValue(LoadUnit.b32Address.storage, self.b32DRAMLoadAddress.storage),
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NextValue(self.LU_CacheOffset, 0), # Adjust pointer (local reader), 4-byte width=32-bit
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NextValue(self.LU_CacheDelay, 2), # Reset load delay counter (but inkl. 1st & last cycle)
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NextState("LU_LOAD1")
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).Elif(~self.bEnable.storage, # Cleared enable?
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NextValue(self.LU_CacheValid, False), # Enforce cache invalidation!
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)
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)
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LU_fsm.act("LU_LOAD1", # Engage!
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NextValue(LoadUnit.bEnable.storage, 1), # Trigger DRAM transfer to cache
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NextState("LU_LOAD2")
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)
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LU_fsm.act("LU_LOAD2", # Wait for termination of transfer ...
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If(LoadUnit.bValid.storage, # Data avail.?
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NextValue(self.LU_CacheValid, 1), # Declare cache valid
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NextValue(LoadUnit.bEnable.storage, 0), # Stop DRAM transfer to cache
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NextState("LU_IDLE") # Yap!
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).Else(
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If(self.LU_CacheDelay < 2047, # MAX-1!
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NextValue(self.LU_CacheDelay, self.LU_CacheDelay + 1),
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)
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# TODO: Permit timeout indication ...
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)
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)
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#---------------- bfloat16 FPU -------------------------------------------------------------
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self.submodules.fpu = fpu = bfloat16Processor() # Integrate bfloat16 FPU
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#---------------- Loaded data testing --------------------------------------------------
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Loader_fsm = FSM(reset_state="Loader_IDLE") # FSM starts idling ...
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self.submodules += Loader_fsm
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self.Loader_Delay = Signal(32, reset_less=True)
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self.Loader_Active = Signal()
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Loader_fsm.act("Loader_IDLE",
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If(self.LU_CacheValid & ~self.Loader_Active, # Enter if not active already
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NextValue(self.Loader_Active, True), # Loader up & running
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NextValue(self.Loader_Delay, 0), # Reset read delay timer
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NextValue(LoadUnit.b9Offset.storage, LUCacheSize - 1), # Adjust offset to read sentinel
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NextValue(self.b16Result.storage, 0), # Indicate # delays
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NextValue(self.b16Status.storage[0], True), # Current status
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NextValue(self.b16Value1.storage, 0), # Nothing loaded so far ...
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NextValue(self.b16Value2.storage, 0), # Nothing loaded so far ...
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NextValue(self.b16Value3.storage, 0), # Nothing loaded so far ...
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NextValue(self.bReady, False), # LED off!
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NextState("Loader_LOAD1")
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).Elif(~self.bEnable.storage, # Externally aborted?
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NextValue(self.b16Status.storage, 0), # Current status: inactive
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NextValue(self.Loader_Active, False), # Reset in sync w/ global activation
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)
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)
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Loader_fsm.act("Loader_LOAD1",
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NextValue(self.b16Status.storage[1], True), # Current status added
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If(LoadUnit.b32Data.storage == self.b32Sentinel.storage, # Valid last entry?
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NextValue(LoadUnit.b9Offset.storage, 0), # 1st value offset preparation
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NextState("Loader_LOAD2")
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).Elif(~self.bEnable.storage, # Enable withdrawn?
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NextState("Loader_IDLE") # Abort!
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)
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)
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Loader_fsm.act("Loader_LOAD2",
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NextValue(self.b16Status.storage[2], True), # Current status added
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If(self.Loader_Delay > RAMWaitTime,
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NextValue(self.b16Value1.storage, LoadUnit.b32Data.storage & 0xFFFF), # Pick 1st date
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NextValue(self.b16Value2.storage, LoadUnit.b32Data.storage >> 16), # Pick 2nd date
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NextValue(fpu.fs1, Cat(0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, LoadUnit.b32Data.storage[0:16])),
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NextValue(fpu.fs2, Cat(0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, LoadUnit.b32Data.storage[16:32])),
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NextValue(LoadUnit.b9Offset.storage, 1), # 2nd value offset preparation
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NextValue(self.Loader_Delay, 0), # Reset delay
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NextState("Loader_LOAD3")
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).Else( # MEM wait cycles
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NextValue(self.Loader_Delay, self.Loader_Delay + 1), # Increment
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)
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)
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Loader_fsm.act("Loader_LOAD3",
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NextValue(self.b16Status.storage[3], True), # Current status added
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If(self.Loader_Delay > RAMWaitTime,
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NextValue(self.b16Value3.storage, LoadUnit.b32Data.storage & 0xFFFF), # Pick 3rd date
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NextValue(fpu.fs3, Cat(0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, LoadUnit.b32Data.storage[0:16])),
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NextState("Loader_EXEC1")
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).Else( # MEM wait cycles
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NextValue(self.Loader_Delay, self.Loader_Delay + 1), # Increment
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)
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)
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"""
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fpu.fnmadd
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fpu.fnmsub
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"""
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Loader_fsm.act("Loader_EXEC1",
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NextValue(self.b16Status.storage[5], True), # Current status added
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NextValue(fpu.fmsub, True), # This command requested
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NextValue(fpu.fready, False), # Engage trigger
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NextState("Loader_EXEC2")
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)
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Loader_fsm.act("Loader_EXEC2",
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NextValue(self.b16Status.storage[6], True), # Current status added
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If(fpu.fready,
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NextValue(fpu.fmsub, False), # Clear command request
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NextValue(self.b16Result.storage, fpu.fresult[16:32]), # Pick result (little endian, high word!)
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NextValue(self.b16Status.storage[15], True), # Indicate readyness ...
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NextValue(self.bReady, True), # Indicate readyness (LED on!)
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NextState("Loader_IDLE")
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)
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)
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