@ -8,7 +8,6 @@
# History:
# --------
# 22.04.21/KQ Initial version
# 03.05.21/KQ FMADD1 state bugs fixed (fs1/fs2 not prepared?)
#
from migen import *
@ -77,11 +76,7 @@ class bfloat16Processor(Module):
NextValue ( self . sign2 , self . fs2 [ 31 ] ^ self . fsub ) , # Invert sign for subtraction!
NextValue ( self . e1 , self . fs1 [ 23 : 31 ] - 127 ) ,
NextValue ( self . e2 , self . fs2 [ 23 : 31 ] - 127 ) ,
#NextValue(self.m1, Cat(0,0,0, self.fs1[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
#NextValue(self.m1, Cat(0,0,0, self.fs1[0:7], 1, 0)), # | 0x00800000 + R/G/S bits FIXME!
NextValue ( self . m1 , Cat ( 0 , 0 , 0 , self . fs1 [ 16 : 23 ] , 1 , 0 ) ) , # | 0x00800000 + R/G/S bits
#NextValue(self.m2, Cat(0,0,0, self.fs2[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
#NextValue(self.m2, Cat(0,0,0, self.fs2[0:7], 1, 0)), # | 0x00800000 + R/G/S bits FIXME!
NextValue ( self . m2 , Cat ( 0 , 0 , 0 , self . fs2 [ 16 : 23 ] , 1 , 0 ) ) , # | 0x00800000 + R/G/S bits
NextState ( " FADD1 " )
) . Elif ( ( self . fmin | self . fmax | self . fmadd | self . fmsub | self . fnmadd | self . fnmsub | self . fmul | self . fdiv ) & ~ self . fready , # Triggers set & ready flag reset externally!
@ -89,11 +84,7 @@ class bfloat16Processor(Module):
NextValue ( self . sign2 , self . fs2 [ 31 ] ) ,
NextValue ( self . e1 , self . fs1 [ 23 : 31 ] - 127 ) ,
NextValue ( self . e2 , self . fs2 [ 23 : 31 ] - 127 ) ,
#NextValue(self.m1, Cat(self.fs1[0:23], 1, 0)), # | 0x00800000
#NextValue(self.m1, Cat(self.fs1[0:7], 1, 0, 0,0,0)), # | 0x00800000 FIXME!
NextValue ( self . m1 , Cat ( self . fs1 [ 16 : 23 ] , 1 , 0 , 0 , 0 , 0 ) ) , # | 0x00800000
#NextValue(self.m2, Cat(self.fs2[0:23], 1, 0)), # | 0x00800000
#NextValue(self.m2, Cat(self.fs2[0:7], 1, 0, 0,0,0)), # | 0x00800000 FIXME!
NextValue ( self . m2 , Cat ( self . fs2 [ 16 : 23 ] , 1 , 0 , 0 , 0 , 0 ) ) , # | 0x00800000
If ( self . fdiv , # Division
NextState ( " FDIV1 " ) ,
@ -107,8 +98,6 @@ class bfloat16Processor(Module):
) . Elif ( self . fsqrt & ~ self . fready , # Trigger set & ready flag reset externally!
NextValue ( self . sign1 , self . fs1 [ 31 ] ) ,
NextValue ( self . e1 , self . fs1 [ 23 : 31 ] - 127 ) ,
#NextValue(self.m1, Cat(self.fs1[0:23], 1, 0)), # | 0x00800000
#NextValue(self.m1, Cat(self.fs1[0:7], 1, 0, 0,0,0)), # | 0x00800000 FIXME!
NextValue ( self . m1 , Cat ( self . fs1 [ 16 : 23 ] , 1 , 0 , 0 , 0 , 0 ) ) , # | 0x00800000
NextState ( " FSQRT1 " ) ,
)
@ -341,24 +330,15 @@ class bfloat16Processor(Module):
)
) # End of fmul.s processing
FPU_fsm . act ( " FMADD1 " ,
# sign3/e3/m3 -> sign1/e1/m1, fs3 -> sign2/e2/m2
# Result->fs1: sign3/e3/m3 -> sign1/e1/m1 & fs1 , fs3->fs2: fs3 -> sign2/e2/m2 & fs 2
NextValue ( self . sign1 , self . sign3 ) , # Negate mult. result w/ f<n>xxx
NextValue ( self . sign2 , self . fs3 [ 31 ] ^ ( self . fmsub | self . fnmsub ) ) , # Invert sign for subtraction!
NextValue ( self . e1 , self . e3 ) ,
NextValue ( self . e2 , self . fs3 [ 23 : 31 ] - 127 ) ,
#NextValue(self.m1, Cat(0,0,0, self.m3[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
#NextValue(self.m1, Cat(0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, self.m3[0:7], 1, 0)), # | 0x00800000 + R/G/S bits
NextValue ( self . m1 , Cat ( 0 , 0 , 0 , self . m3 [ 0 : 7 ] , 1 , 0 ) ) , # | 0x00800000 + R/G/S bits
#NextValue(self.m2, Cat(0,0,0, self.fs3[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
#NextValue(self.m2, Cat(0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, self.fs3[16:23], 1, 0)), # | 0x00800000 + R/G/S bits
NextValue ( self . m2 , Cat ( 0 , 0 , 0 , self . fs3 [ 16 : 23 ] , 1 , 0 ) ) , # | 0x00800000 + R/G/S bits
# sign3/e3/m3 -> fs1 (reconstruction, nec. for compares, s.a.!)
NextValue ( self . m2 , Cat ( 0 , 0 , 0 , self . fs3 [ 16 : 23 ] , 1 , 0 ) ) , # | 0x00800000 + R/G/S bits
NextValue ( self . fs1 , Cat ( 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , self . m3 [ 0 : 7 ] , ( self . e3 + 127 ) [ 0 : 8 ] , self . sign3 ) ) ,
# fs3 -> fs2
NextValue ( self . fs2 , self . fs3 ) ,
NextState ( " FADD1 " ) # Add fs1 & fs2!
)