2 transfers, working (but wrong solution!)

master
kaqu 1 year ago
parent 8ae7085df7
commit c0189b15c7
  1. 4
      bfloat16nn.py
  2. 107
      libmodules/bfloat16nncore.py
  3. 46
      libmodules/dramtransfer.py
  4. 170
      software/source/bfloat16nnlib.c

@ -183,7 +183,7 @@ class BaseSoC(SoCCore):
self.add_csr("systime")
# DRAM access section
MAXWORDS = 512 #512 # Transfer length 32 x 32-bit, FIFO depth (511 L1 cache currently possible = 9-bit!)
MAXWORDS = 512 # Max. FIFO!
# Load unit memory access
self.submodules.dma_reader = dma_reader = LiteDRAMDMAReader(self.sdram.crossbar.get_port(), fifo_depth=MAXWORDS, fifo_buffered=True)
dma_reader.add_csr()
@ -209,7 +209,7 @@ class BaseSoC(SoCCore):
self.add_csr("fpga2dram")
"""
# Integrate bfloat16NN processor
RAMWAITTIME=1 # Minimum wait!
RAMWAITTIME = 1 # Minimum wait!
self.submodules.bfloat16nn = bfloat16nn = bfloat16NeuralNetworkCore(
RAMWaitTime=RAMWAITTIME,
LUCacheSize=MAXWORDS,

@ -42,11 +42,11 @@ class bfloat16NeuralNetworkCore(Module, AutoCSR, AutoDoc, ModuleDoc):
:b32DRAMAddress: New DRAM address from where to load into local memory
:b32Sentinel: Write control word to last address (same as [b32DRAMAddress+511] value)
:b32Sentinel: Write control word to last address (same as [b32DRAMAddress+LEN-1] value)
:bEnable: To enable running (after data preparation)
:b9ArrayWordLen: Number of words used for calculation of scalar (inner) product
:b10ArrayWordLen: Number of words used for calculation of scalar (inner) product
Outputs:
########
@ -78,8 +78,8 @@ class bfloat16NeuralNetworkCore(Module, AutoCSR, AutoDoc, ModuleDoc):
description="""
Enable free run
""")
self.b9ArrayWordLen = CSRStorage(9, reset_less=False,
fields=[CSRField("ArrayWordLen", size=9, description="*Field*: 9-Bit value")],
self.b10ArrayWordLen = CSRStorage(10, reset_less=False,
fields=[CSRField("ArrayWordLen", size=10, description="*Field*: 10-Bit value")],
description="""
Word length of array used for calculation
""")
@ -95,28 +95,6 @@ class bfloat16NeuralNetworkCore(Module, AutoCSR, AutoDoc, ModuleDoc):
description="""
FPU states: Low FPU#1, High FPU#2
""")
""" TODO: Remove!
self.b16Value1_1 = CSRStorage(16, reset_less=False,
fields=[CSRField("Value", size=16, description="*Field*: 16-Bit value")],
description="
FPU#1 Float register 1
")
self.b16Value1_2 = CSRStorage(16, reset_less=False,
fields=[CSRField("Value", size=16, description="*Field*: 16-Bit value")],
description="
#FPU#1 Float register 2
")
self.b16Value2_1 = CSRStorage(16, reset_less=False,
fields=[CSRField("Value", size=16, description="*Field*: 16-Bit value")],
description="
#FPU#2 Float register 1
")
self.b16Value2_2 = CSRStorage(16, reset_less=False,
fields=[CSRField("Value", size=16, description="*Field*: 16-Bit value")],
description=" " "
#FPU#2 Float register 2
" " ")
"""
self.b16Result1 = CSRStorage(16, reset_less=False,
fields=[CSRField("Result1", size=16, description="*Field*: 16-Bit value")],
description="""
@ -130,13 +108,13 @@ class bfloat16NeuralNetworkCore(Module, AutoCSR, AutoDoc, ModuleDoc):
self.bReady = Signal() # To be wired to data pin ... ;)
# Local vars.
# - none yet -
self.b10CurrentOffest = Signal(10, reset_less=True)
#---------------- Load unit (LU) -------------------------------------------------------------
LU_fsm = FSM(reset_state="LU_IDLE") # FSM starts idling ...
self.submodules += LU_fsm
self.LU_CacheOffset = Signal(9, reset_less=True) # 0..511 log2_int(LUCacheSize, False)) # Cache reading offset (0..(Size-1))=>Bits)
self.LU_CacheOffset = Signal(10, reset_less=True) # 0..1023 log2_int(LUCacheSize, False)) # Cache reading offset (0..(Size-1))=>Bits)
self.LU_CacheValid = Signal() # Indicate loaded LU cache
self.LU_CacheDelay = Signal(11, reset_less=True) # Evaluate load length in cycles (2048 max.)
LU_fsm.act("LU_IDLE", # If cache not valid fill it!
@ -181,14 +159,11 @@ class bfloat16NeuralNetworkCore(Module, AutoCSR, AutoDoc, ModuleDoc):
If(self.LU_CacheValid & ~self.Loader_Active, # Enter if not active already
NextValue(self.Loader_Active, True), # Loader up & running
NextValue(self.Loader_Delay, 0), # Reset read delay timer
NextValue(LoadUnit.b9Offset1.storage, LUCacheSize - 1), # Adjust offset to read sentinel
NextValue(LoadUnit.b9Offset2.storage, LUCacheSize >> 1), # Adjust offset to start of 2nd array
NextValue(self.b10CurrentOffest, 0), # Actual offset (=DRAM local offset)
NextValue(LoadUnit.b10Offset1.storage, LUCacheSize - 1), # Adjust offset to read sentinel
NextValue(LoadUnit.b10Offset2.storage, LUCacheSize >> 1), # Adjust offset to start of 2nd array
NextValue(self.b16Result1.storage, 0), # Indicate # delays
NextValue(self.b16Result2.storage, 0), # Indicate # delays
#NextValue(self.b16Value1_1.storage, 0), # TODO: Remove! Nothing loaded so far ...
#NextValue(self.b16Value1_2.storage, 0),
#NextValue(self.b16Value2_1.storage, 0),
#NextValue(self.b16Value2_2.storage, 0),
NextValue(self.bReady, False), # LED off!
NextState("Loader_LOAD1")
).Elif(~self.bEnable.storage, # Externally aborted?
@ -197,9 +172,9 @@ class bfloat16NeuralNetworkCore(Module, AutoCSR, AutoDoc, ModuleDoc):
)
)
Loader_fsm.act("Loader_LOAD1",
NextValue(self.b16Status.storage[0], True), # Current status added
NextValue(self.b16Status.storage[0], True), # Current status added
If(LoadUnit.b32Data1.storage == self.b32Sentinel.storage, # Valid last entry?
NextValue(LoadUnit.b9Offset1.storage, 0), # 1st value offset preparation
NextValue(LoadUnit.b10Offset1.storage, 0), # 1st value offset preparation
NextState("Loader_LOAD2")
).Elif(~self.bEnable.storage, # Enable withdrawn?
NextState("Loader_IDLE") # Abort!
@ -210,18 +185,16 @@ class bfloat16NeuralNetworkCore(Module, AutoCSR, AutoDoc, ModuleDoc):
Loader_fsm.act("Loader_LOAD2",
NextValue(self.b16Status.storage[1], True), # Current status added
If(self.Loader_Delay > RAMWaitTime, # Required only for 1st entry ...
NextValue(self.b10CurrentOffest, self.b10CurrentOffest + 1), # Increment (total) offset
# FPU#1
#NextValue(self.b16Value1_1.storage, LoadUnit.b32Data1.storage & 0xFFFF), # TODO: Remove! Pick 1st date
#NextValue(self.b16Value1_2.storage, LoadUnit.b32Data1.storage >> 16), # TODO: Remove! Pick 2nd date
NextValue(fpu1.fs1, Cat(0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, LoadUnit.b32Data1.storage[0:16])),
NextValue(fpu1.fs2, Cat(0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, LoadUnit.b32Data1.storage[16:32])),
NextValue(LoadUnit.b9Offset1.storage, LoadUnit.b9Offset1.storage + 1), # Move on to next entry
NextValue(LoadUnit.b10Offset1.storage, LoadUnit.b10Offset1.storage + 1), # Move on to next entry
# FPU#2
#NextValue(self.b16Value2_1.storage, LoadUnit.b32Data2.storage & 0xFFFF), # TODO: Remove! Pick 1st date
#NextValue(self.b16Value2_2.storage, LoadUnit.b32Data2.storage >> 16), # TODO: Remove! Pick 2nd date
NextValue(fpu2.fs1, Cat(0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, LoadUnit.b32Data2.storage[0:16])),
NextValue(fpu2.fs2, Cat(0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, LoadUnit.b32Data2.storage[16:32])),
NextValue(LoadUnit.b9Offset2.storage, LoadUnit.b9Offset2.storage + 1), # Move on to next entry
NextValue(LoadUnit.b10Offset2.storage, LoadUnit.b10Offset2.storage + 1), # Move on to next entry
NextState("Loader_EXEC1")
).Else( # MEM wait cycles
@ -230,7 +203,7 @@ class bfloat16NeuralNetworkCore(Module, AutoCSR, AutoDoc, ModuleDoc):
)
Loader_fsm.act("Loader_EXEC1",
NextValue(self.b16Status.storage[2], True), # Current status added
If(LoadUnit.b9Offset1.storage == 1, # As pointer already moved ahead 1!
If(LoadUnit.b10Offset1.storage == 1, # As pointer already moved ahead 1!
NextValue(fpu1.fmul, True), # 1st ADD requested
NextValue(fpu2.fmul, True),
).Else(
@ -246,7 +219,7 @@ class bfloat16NeuralNetworkCore(Module, AutoCSR, AutoDoc, ModuleDoc):
NextValue(self.b16Status.storage[8], fpu1.fready), # TODO: Remove!
NextValue(self.b16Status.storage[9], fpu2.fready), # TODO: Remove!
If(fpu1.fready & fpu2.fready,
If(LoadUnit.b9Offset1.storage == 1, # As pointer already moved ahead 1! (Actually: Entry #0)
If(LoadUnit.b10Offset1.storage == 1, # As pointer already moved ahead 1! (Actually: Entry #0)
NextValue(fpu1.fmul, False), # Clear command request FPU#1
NextValue(fpu2.fmul, False), # Clear command request FPU#2
).Else( # Entries 1 .. (maxlen-1)
@ -254,24 +227,58 @@ class bfloat16NeuralNetworkCore(Module, AutoCSR, AutoDoc, ModuleDoc):
NextValue(fpu2.fmadd, False), # Clear command request FPU#2
),
NextValue(fpu1.fs3, Cat(0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, fpu1.fresult[16:32])), # Sum will be used for fmadd.s
NextValue(fpu2.fs3, Cat(0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, fpu2.fresult[16:32])), # Sum will be used for fmadd.s
If(LoadUnit.b9Offset1.storage < self.b9ArrayWordLen.storage, # Words 0 .. 255
NextState("Loader_LOAD2")
NextValue(fpu2.fs3, Cat(0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, fpu2.fresult[16:32])), # Sum will be used for fmadd.s
If(self.b10CurrentOffest < self.b10ArrayWordLen.storage, # Words 0 .. LEN-1
If(LoadUnit.b10Offset1.storage < LUCacheSize, # Words 0 .. Cachelen
NextState("Loader_LOAD2") # Next value @offset
).Else( # Cache empty ...
NextValue(self.b32DRAMLoadAddress.storage, self.b32DRAMLoadAddress.storage + LUCacheSize), # Prepare DRAM address
NextState("Loader_XLOAD0") # Fill cache again
)
).Else( # Finally prepare ADD both result sums (on FPU#1 only!)
NextValue(fpu1.fs1, fpu1.fresult),
NextValue(fpu1.fs2, fpu2.fresult),
NextState("Loader_EXEC3")
NextState("Loader_EXEC3") # -> Final ADD logic & finishing cleanup
)
)
)
# Extended (2nd) cache load
Loader_fsm.act("Loader_XLOAD0",
NextValue(self.b16Status.storage[4], True), # Current status added
NextValue(self.LU_CacheValid, 0), # Engage refill (address safely adjusted by now ...)
NextState("Loader_XLOAD1")
)
Loader_fsm.act("Loader_XLOAD1", # Extended load ...
NextValue(self.b16Status.storage[5], True), # Current status added
If(self.LU_CacheValid, # Wait until filled ...
#NextValue(self.Loader_Delay, 0), # Reset read delay timer
NextValue(LoadUnit.b10Offset1.storage, LUCacheSize - 1), # Adjust offset to read sentinel
NextValue(LoadUnit.b10Offset2.storage, LUCacheSize >> 1), # Adjust offset to start of 2nd array
NextState("Loader_XLOAD2")
).Elif(~self.bEnable.storage, # Externally aborted?
NextState("Loader_IDLE") # Abort!
)
)
Loader_fsm.act("Loader_XLOAD2",
NextValue(self.b16Status.storage[6], True), # Current status added
If(LoadUnit.b32Data1.storage == (self.b32Sentinel.storage + 1), # Valid last entry? +1!!!
NextValue(LoadUnit.b10Offset1.storage, 0), # 1st value offset preparation
NextState("Loader_LOAD2") # Continue w/ loop
).Elif(~self.bEnable.storage, # Enable withdrawn?
NextState("Loader_IDLE") # Abort!
)
)
# Final ADD of results
Loader_fsm.act("Loader_EXEC3",
NextValue(self.b16Status.storage[4], True), # Current status added
NextValue(self.b16Status.storage[7], True), # Current status added
NextValue(fpu1.fadd, True), # Final ADD requested
NextValue(fpu1.fready, False), # Engage trigger FPU#1 (only!)
NextState("Loader_EXEC4")
)
Loader_fsm.act("Loader_EXEC4",
NextValue(self.b16Status.storage[5], True), # Current status added
NextValue(self.b16Status.storage[8], True), # Current status added
If(fpu1.fready,
NextValue(fpu1.fadd, False), # Clear command request FPU#1
NextValue(self.b16Result1.storage, fpu1.fresult[16:32]), # Pick result (little endian, high word!)

@ -36,7 +36,7 @@ class DRAM2FPGA(Module, AutoCSR, AutoDoc, ModuleDoc):
#. Once ``bValid`` becomes true (1), FPGA local memory is loaded, deactivate ``bEnable``
#. To retrieve, load ``b9Offset`` with offset (from base adress) to read from (0 .. 511),
#. To retrieve, load ``b10Offset`` with offset (from base adress) to read from (0 .. 1023),
``b32Data`` will contain the 32-bit value (from local FPGA memory @offset)
Inputs:
@ -46,18 +46,18 @@ class DRAM2FPGA(Module, AutoCSR, AutoDoc, ModuleDoc):
:bEnable: To enable running (after initialization)
:b9Offset1: Offset #1 (0..511) into local FPGA memory to read from
:b10Offset1: Offset #1 (0..1023) into local FPGA memory to read from
:b9Offset2: Offset #2 (0..511) into local FPGA memory to read from
:b10Offset2: Offset #2 (0..1023) into local FPGA memory to read from
Output:
#######
:bValid: Indicate validity of local FPGA memory, i.e. 'loaded'
:b32Data1: Local FPGA memory at b9Offset1
:b32Data1: Local FPGA memory at b10Offset1
:b32Data2: Local FPGA memory at b9Offset2
:b32Data2: Local FPGA memory at b10Offset2
"""
def __init__(self, maxwords=8, dma_reader=None, sync_fifo=None):
@ -76,13 +76,13 @@ class DRAM2FPGA(Module, AutoCSR, AutoDoc, ModuleDoc):
description="""
Enable/disabling DRAM access
""")
self.b9Offset1 = CSRStorage(9, reset_less=True,
fields=[CSRField("Offset1", size=9, description="*Field*: 9-Bit value (0..511)")],
self.b10Offset1 = CSRStorage(10, reset_less=True,
fields=[CSRField("Offset1", size=10, description="*Field*: 10-Bit value (0..1023)")],
description="""
Offset added to base address, port #1
""")
self.b9Offset2 = CSRStorage(9, reset_less=True,
fields=[CSRField("Offset2", size=9, description="*Field*: 9-Bit value (0..511)")],
self.b10Offset2 = CSRStorage(10, reset_less=True,
fields=[CSRField("Offset2", size=10, description="*Field*: 10-Bit value (0..1023)")],
description="""
Offset added to base address, port #2
""")
@ -190,32 +190,32 @@ class DRAM2FPGA(Module, AutoCSR, AutoDoc, ModuleDoc):
rdport2 = storage.get_port()
self.specials += rdport2
self.comb += [ # Read from (FPGA local) memory
self.b2Address1.eq(self.b9Offset1.storage[0:2]), # Filter bits 0..1 (range 0-3)
If(self.b9Offset1.storage < maxwords,
#rdport.adr.eq(self.b9Offset1.storage), # w/ translation!
self.b2Address1.eq(self.b10Offset1.storage[0:2]), # Filter bits 0..1 (range 0-3)
If(self.b10Offset1.storage < maxwords,
#rdport.adr.eq(self.b10Offset1.storage), # w/ translation!
If(self.b2Address1 == 0,
rdport1.adr.eq(self.b9Offset1.storage | 3) # 0->3
rdport1.adr.eq(self.b10Offset1.storage | 3) # 0->3
).Elif(self.b2Address1 == 1,
rdport1.adr.eq((self.b9Offset1.storage & 0x1FC) | 2) # 1->2
rdport1.adr.eq((self.b10Offset1.storage & 0x1FC) | 2) # 1->2
).Elif(self.b2Address1 == 2,
rdport1.adr.eq((self.b9Offset1.storage & 0x1FC) | 1) # 2->1
rdport1.adr.eq((self.b10Offset1.storage & 0x1FC) | 1) # 2->1
).Elif(self.b2Address1 == 3,
rdport1.adr.eq(self.b9Offset1.storage & 0x1FC) # 3->0
rdport1.adr.eq(self.b10Offset1.storage & 0x1FC) # 3->0
),
self.bData1.eq(rdport1.dat_r) # Assign to external var. ...
),
self.b2Address2.eq(self.b9Offset2.storage[0:2]), # Filter bits 0..1 (range 0-3)
If(self.b9Offset2.storage < maxwords,
#rdport.adr.eq(self.b9Offset2.storage), # w/ translation!
self.b2Address2.eq(self.b10Offset2.storage[0:2]), # Filter bits 0..1 (range 0-3)
If(self.b10Offset2.storage < maxwords,
#rdport.adr.eq(self.b10Offset2.storage), # w/ translation!
If(self.b2Address2 == 0,
rdport2.adr.eq(self.b9Offset2.storage | 3) # 0->3
rdport2.adr.eq(self.b10Offset2.storage | 3) # 0->3
).Elif(self.b2Address2 == 1,
rdport2.adr.eq((self.b9Offset2.storage & 0x1FC) | 2) # 1->2
rdport2.adr.eq((self.b10Offset2.storage & 0x1FC) | 2) # 1->2
).Elif(self.b2Address2 == 2,
rdport2.adr.eq((self.b9Offset2.storage & 0x1FC) | 1) # 2->1
rdport2.adr.eq((self.b10Offset2.storage & 0x1FC) | 1) # 2->1
).Elif(self.b2Address2 == 3,
rdport2.adr.eq(self.b9Offset2.storage & 0x1FC) # 3->0
rdport2.adr.eq(self.b10Offset2.storage & 0x1FC) # 3->0
),
self.bData2.eq(rdport2.dat_r) # Assign to external var. ...
),

@ -45,33 +45,46 @@ extern char kbhit(void);
extern int key_eval(void);
#define DRAMDATABASE 0x40190000
#define DRAMDATASIZE 512
#define DRAMDATASIZE 1024 // 512 OK, 800 FAIL => 2 Load cycles (2*512)!
static uint32_t fpgastate, fpustates;
static int fpgaload(uint32_t *mempt, int16_t len, int16_t calclen)
{
uint32_t *sentinel = (uint32_t *)(DRAMDATABASE + (DRAMDATASIZE - 1) * sizeof(int32_t));
uint32_t *sentinel1 = (uint32_t *)(DRAMDATABASE + (DRAMDATASIZE/2 - 1) * sizeof(int32_t));
uint32_t *sentinel2 = (uint32_t *)(DRAMDATABASE + (DRAMDATASIZE - 1) * sizeof(int32_t));
if((len < 4) | (len > 512)) return -1; // Verify length of transfer was understood!
if((calclen < 2) | (calclen > len/2)) return -2; // Reasonable calc amount?
if((len < 4) | (len > DRAMDATASIZE)) {
printf("*** fpgaload: len out of range!");
return -1; // Verify length of transfer was understood!
}
if((calclen < 2) | (calclen > len/2)) {
printf("*** fpgaload: calclen out of range!");
return -2; // Reasonable calc amount?
}
bfloat16nn_bEnable_write(0); // Disable transfer (if still active for some reason ...)
*sentinel1 = 0x41434142; // Just some marker pattern ;)
*sentinel2 = 0x41434142 + 1; // Just some marker pattern ;)
bfloat16nn_b32Sentinel_write(*sentinel1);
flush_l2_cache(); // Strictly nec. for longer transfers
bfloat16nn_b9ArrayWordLen_write(calclen); // Indicate array length for calc.
bfloat16nn_b10ArrayWordLen_write(calclen); // Indicate array length for calc.
bfloat16nn_b32DRAMLoadAddress_write((uint32_t)mempt); // Indicate memory to load from
//*sentinel = 0xAAFF01A3;
bfloat16nn_b32Sentinel_write(*sentinel);
bfloat16nn_bEnable_write(1); // Finally: Engage!
for(int i=0;i<10;i++) { // Max. 100ms delay
for(int i=0;i<2000;i++) { // Max. 100ms delay
if(bfloat16nn_b16Status_read() & 0x8000) {
bfloat16nn_bEnable_write(0); // Disable transfer
fpgastate = 0;
fpustates = 0;
return 1; // Ok, ready!
}
else
busy_wait(10); // Just wait some time ...
busy_wait(1); // Just wait some time ...
}
fpgastate = (uint32_t)bfloat16nn_b16Status_read();
fpustates = (uint32_t)bfloat16nn_b16FPUStates_read();
bfloat16nn_bEnable_write(0); // Disable transfer
return 0; // Timeout
}
/*
static float fp1_1_read(void)
{
uint32_t v __attribute__((aligned(16))) = 0;
@ -100,6 +113,7 @@ static float fp2_2_read(void)
float *fpt = (float *)&v;
return *fpt;
}
*/
static float fpResult1_read(void)
{
uint32_t v __attribute__((aligned(16))) = 0;
@ -134,17 +148,44 @@ int key_eval(void)
uint32_t *ui32ptr;
uint16_t *ui16ptr1, *ui16ptr2;
int i;
float fp1_1, fp1_2, fpResult1;
float fp2_1, fp2_2, fpResult2;
//float fp1_1, fp1_2;
float fpResult1;
//float fp2_1, fp2_2;
float fpResult2;
uint32_t starttime;
uint32_t deltatime;
#define MAXCALCLEN 16
#define MAXCALCLEN (284) //784 //16 OK
switch(kbhit()) {
case 'r': // Reload
printf("\e[35;1m*** Reload ***\e[0m\n");
printf("Elements/FPU: %d\n", MAXCALCLEN);
for(i=0, ui32ptr = (uint32_t *)DRAMDATABASE;i<DRAMDATASIZE;i++) // Setup test data
*ui32ptr++ = 0; // Clear all memory ...
for(i=0, ui32ptr = (uint32_t *)DRAMDATABASE;i<DRAMDATASIZE;i++) // Setup test data
*ui32ptr++ = i+1; // Clear all memory ...
/*
// TODO: Control procedure w/ regular code (matrice inner product)
float *floatptr = (float *)DRAMDATABASE;
float *floatptr2 = (float *)(DRAMDATABASE + (MAXCALCLEN/2) * sizeof(float)); // Absolute: bytes!
for(i=1;i<=MAXCALCLEN/2;i++) {
*floatptr++ = (1.0 * (float)i);
*floatptr2++ = (1.0 * (float)i);
}
floatptr = (float *)DRAMDATABASE;
floatptr2 = (float *)(DRAMDATABASE + (MAXCALCLEN/2) * sizeof(float)); // Absolute: bytes!
starttime = systime(0);
float sum = 0.0;
for(i=1;i<=MAXCALCLEN/2;i++) {
sum += ((*floatptr++) * (*floatptr2++)); // 1*1+2*2+3*3+4*4 = 1+4+9+16 = 5+9+16 = 14+16=30
}
deltatime = systime(0)-starttime;
printf("S/W Delta t: %dms ", deltatime);
printf1("\t\t\tS/W SUM=%8.4f\n", sum);
// FPU#1
ui16ptr1 = (uint16_t *)(DRAMDATABASE + 0 * sizeof(uint32_t)); // Absolute: bytes!
for(i=1;i<=MAXCALCLEN;i++)
@ -154,77 +195,94 @@ int key_eval(void)
ui16ptr2 = (uint16_t *)(DRAMDATABASE + (DRAMDATASIZE/2) * sizeof(uint32_t)); // Absolute: bytes!
for(i=1;i<=MAXCALCLEN;i++)
*ui16ptr2++ = f2ui16(1.0 * (float)i );
// TODO: Control procedure w/ regular code (matrice inner product)
float sum = 0.0;
for(i=1;i<=MAXCALCLEN;i+=2) {
sum += (1.0 * (float)i) * (1.0 * (float)(i+1));
}
sum *= 2.0; // Sim. 2 FPUs!
printf("Elements/FPU: %d", MAXCALCLEN);
printf1(" S/W SUM (2xFPU): %8.3f\n", sum);
if(fpgaload((uint32_t *)DRAMDATABASE, 512, MAXCALCLEN)) { // 512*32-bit=2048 bytes = 2kB, 256 Words/FPU to calc.
fp1_1 = fp1_1_read();
*/
starttime = systime(0);
if(fpgaload((uint32_t *)DRAMDATABASE, DRAMDATASIZE, MAXCALCLEN/2)) { // 800*32-bit=3200 bytes, 400 Words/FPU to calc.
deltatime = systime(0)-starttime;
printf("H/W Delta t: %dms ", deltatime);
/*fp1_1 = fp1_1_read();
fp1_2 = fp1_2_read();
fp2_1 = fp2_1_read();
fp2_2 = fp2_2_read();
fp2_2 = fp2_2_read();*/
fpResult1 = fpResult1_read();
fpResult2 = fpResult2_read();
printf("S=%04Xh: FS=%04Xh\n", (uint32_t)bfloat16nn_b16Status_read(), (uint32_t)bfloat16nn_b16FPUStates_read());
printf1("V1_1=%6.3f ", fp1_1);
printf1("V1_2=%6.3f ", fp1_2);
printf1("TOTAL SUM=%8.4f\n", fpResult1);
printf1("V2_1=%6.3f ", fp2_1);
printf1("V2_2=%6.3f ", fp2_2);
printf1("RESULT2=%8.4f\n", fpResult2);
printf("(S=%04Xh: FS=%04Xh)", fpgastate, fpustates);
/*printf1("V1_1=%6.3f ", fp1_1);
printf1("V1_2=%6.3f ", fp1_2);*/
printf1("\tS/W SUM=%8.4f\n", fpResult1);
/*printf1("V2_1=%6.3f ", fp2_1);
printf1("V2_2=%6.3f ", fp2_2);*/
//printf1("(RESULT2=%8.4f)", fpResult2);
/*
for(i=DRAMDATASIZE/2;i<DRAMDATASIZE/2+3;i++) {
dram2fpga_b9Offset2_write(i);
dram2fpga_b10Offset2_write(i);
printf("%d: %d\n", i, dram2fpga_b32Data2_read());
}
dram2fpga_b9Offset2_write(DRAMDATASIZE - 1);
dram2fpga_b10Offset2_write(DRAMDATASIZE - 1);
printf("%d: %d\n", DRAMDATASIZE - 1, dram2fpga_b32Data2_read());
*/
}
else {
printf("CURRENT: TIMEOUT! S=%04Xh: FS=%04Xh\n", (uint32_t)bfloat16nn_b16Status_read(), (uint32_t)bfloat16nn_b16FPUStates_read());
printf("Offset 1: %d ", (uint32_t)dram2fpga_b9Offset1_read());
printf("Offset 2: %d\n", (uint32_t)dram2fpga_b9Offset2_read());
printf("CURRENT TIMEOUT: S=%04Xh: FS=%04Xh ", fpgastate, fpustates);
printf("Offset 1: %d (%d) ", (uint32_t)dram2fpga_b10Offset1_read(), dram2fpga_b32Data1_read());
printf("Offset 2: %d (%d)", (uint32_t)dram2fpga_b10Offset2_read(), dram2fpga_b32Data2_read());
printf("Sentinels: %08Xh %08Xh\n", bfloat16nn_b32Sentinel_read(), dram2fpga_b32Data1_read());
for(i=0;i<10;i++) {
dram2fpga_b10Offset1_write(i);
dram2fpga_b10Offset2_write(i);
printf("%d: %d=%d\n", i, dram2fpga_b32Data1_read(), dram2fpga_b32Data2_read());
}
for(i=DRAMDATASIZE/2 - 5;i<(DRAMDATASIZE/2 + 5);i++) {
dram2fpga_b10Offset1_write(i);
dram2fpga_b10Offset2_write(i);
printf("%d: %d=%d\n", i, dram2fpga_b32Data1_read(), dram2fpga_b32Data2_read());
}
for(i=512 - 5;i<(512 + 5);i++) {
dram2fpga_b10Offset1_write(i);
dram2fpga_b10Offset2_write(i);
printf("%d: %d=%d\n", i, dram2fpga_b32Data1_read(), dram2fpga_b32Data2_read());
}
for(i=DRAMDATASIZE-10;i<DRAMDATASIZE-1;i++) {
dram2fpga_b10Offset1_write(i);
dram2fpga_b10Offset2_write(i);
printf("%d: %d=%d\n", i, dram2fpga_b32Data1_read(), dram2fpga_b32Data2_read());
}
dram2fpga_b10Offset1_write(DRAMDATASIZE - 1);
dram2fpga_b10Offset2_write(DRAMDATASIZE - 1);
printf("%d:*%d=%d*\n", DRAMDATASIZE - 1, dram2fpga_b32Data1_read(), dram2fpga_b32Data2_read());
}
*sentinel = 0; // Invalidate data!
if(fpgaload((uint32_t *)DRAMDATABASE, 512, MAXCALCLEN)) {
fp1_1 = fp1_1_read();
if(fpgaload((uint32_t *)DRAMDATABASE, DRAMDATASIZE, MAXCALCLEN/2)) {
/*fp1_1 = fp1_1_read();
fp1_2 = fp1_2_read();
fp2_1 = fp2_1_read();
fp2_2 = fp2_2_read();
fp2_2 = fp2_2_read();*/
fpResult1 = fpResult1_read();
fpResult2 = fpResult2_read();
printf("INVALIDATED: S=%04Xh: FS=%04Xh\n", (uint32_t)bfloat16nn_b16Status_read(), (uint32_t)bfloat16nn_b16FPUStates_read());
printf1("V1_1=%6.3f ", fp1_1);
printf1("V1_2=%6.3f ", fp1_2);
printf1("RESULT1=%8.4f\n", fpResult1);
printf1("V2_1=%6.3f ", fp2_1);
printf1("V2_2=%6.3f ", fp2_2);
printf1("RESULT2=%8.4f\n", fpResult2);
printf("INVALIDATED: S=%04Xh: FS=%04Xh\n", fpgastate, fpustates);
/*printf1("V1_1=%6.3f ", fp1_1);
printf1("V1_2=%6.3f ", fp1_2);*/
//printf1("RESULT1=%8.4f\n", fpResult1);
/*printf1("V2_1=%6.3f ", fp2_1);
printf1("V2_2=%6.3f ", fp2_2);*/
//printf1("RESULT2=%8.4f\n", fpResult2);
}
else
printf("INVALIDATED: S=%04Xh: FS=%04Xh\n", (uint32_t)bfloat16nn_b16Status_read(), (uint32_t)bfloat16nn_b16FPUStates_read());
printf("INVALIDATED TIMEOUT: S=%04Xh: FS=%04Xh\n", fpgastate, fpustates);
break;
case 's':
fp1_1 = fp1_1_read();
/*fp1_1 = fp1_1_read();
fp1_2 = fp1_2_read();
fp2_1 = fp2_1_read();
fp2_2 = fp2_2_read();
fp2_2 = fp2_2_read();*/
fpResult1 = fpResult1_read();
fpResult2 = fpResult2_read();
printf("REQUESTED: S=%04Xh: FS=%04Xh\n", (uint32_t)bfloat16nn_b16Status_read(), (uint32_t)bfloat16nn_b16FPUStates_read());
printf1("V1_1=%6.3f ", fp1_1);
printf1("V1_2=%6.3f ", fp1_2);
/*printf1("V1_1=%6.3f ", fp1_1);
printf1("V1_2=%6.3f ", fp1_2);*/
printf1("RESULT1=%8.4f\n", fpResult1);
printf1("V2_1=%6.3f ", fp2_1);
printf1("V2_2=%6.3f ", fp2_2);
/*printf1("V2_1=%6.3f ", fp2_1);
printf1("V2_2=%6.3f ", fp2_2);*/
printf1("RESULT2=%8.4f\n", fpResult2);
break;
case 'x': return 1; // Abort indication

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