bugs fixed, fmadd ok
kaqu
parent
ea794dfa9c
commit
69b4557926
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@ -201,22 +201,21 @@ class bfloat16NeuralNetworkCore(Module, AutoCSR, AutoDoc, ModuleDoc):
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NextValue(self.Loader_Delay, self.Loader_Delay + 1), # Increment
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)
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)
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"""
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fpu.fmadd
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"""
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fpu.fmsub
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fpu.fnmadd
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fpu.fnmsub
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"""
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Loader_fsm.act("Loader_EXEC1",
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NextValue(self.b16Status.storage[5], True), # Current status added
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NextValue(fpu.fmax, True), # This command requested
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NextValue(fpu.fmadd, True), # This command requested
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NextValue(fpu.fready, False), # Engage trigger
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NextState("Loader_EXEC2")
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)
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Loader_fsm.act("Loader_EXEC2",
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NextValue(self.b16Status.storage[6], True), # Current status added
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If(fpu.fready,
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NextValue(fpu.fmax, False), # Clear command request
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NextValue(fpu.fmadd, False), # Clear command request
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NextValue(self.b16Result.storage, fpu.fresult[16:32]), # Pick result (little endian, high word!)
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NextValue(self.b16Status.storage[15], True), # Indicate readyness ...
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NextValue(self.bReady, True), # Indicate readyness (LED on!)
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@ -8,6 +8,7 @@
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# History:
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# --------
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# 22.04.21/KQ Initial version
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# 03.05.21/KQ FMADD1 state bugs fixed (fs1/fs2 not prepared?)
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#
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from migen import *
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@ -77,9 +78,11 @@ class bfloat16Processor(Module):
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NextValue(self.e1, self.fs1[23:31] - 127),
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NextValue(self.e2, self.fs2[23:31] - 127),
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#NextValue(self.m1, Cat(0,0,0, self.fs1[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
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NextValue(self.m1, Cat(0,0,0, self.fs1[0:7], 1, 0)), # | 0x00800000 + R/G/S bits
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#NextValue(self.m1, Cat(0,0,0, self.fs1[0:7], 1, 0)), # | 0x00800000 + R/G/S bits FIXME!
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NextValue(self.m1, Cat(0,0,0, self.fs1[16:23], 1, 0)), # | 0x00800000 + R/G/S bits
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#NextValue(self.m2, Cat(0,0,0, self.fs2[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
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NextValue(self.m2, Cat(0,0,0, self.fs2[0:7], 1, 0)), # | 0x00800000 + R/G/S bits
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#NextValue(self.m2, Cat(0,0,0, self.fs2[0:7], 1, 0)), # | 0x00800000 + R/G/S bits FIXME!
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NextValue(self.m2, Cat(0,0,0, self.fs2[16:23], 1, 0)), # | 0x00800000 + R/G/S bits
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NextState("FADD1")
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).Elif((self.fmin | self.fmax | self.fmadd | self.fmsub | self.fnmadd | self.fnmsub | self.fmul | self.fdiv) & ~self.fready, # Triggers set & ready flag reset externally!
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NextValue(self.sign1, self.fs1[31]),
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@ -87,9 +90,11 @@ class bfloat16Processor(Module):
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NextValue(self.e1, self.fs1[23:31] - 127),
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NextValue(self.e2, self.fs2[23:31] - 127),
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#NextValue(self.m1, Cat(self.fs1[0:23], 1, 0)), # | 0x00800000
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NextValue(self.m1, Cat(self.fs1[0:7], 1, 0, 0,0,0)), # | 0x00800000
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#NextValue(self.m1, Cat(self.fs1[0:7], 1, 0, 0,0,0)), # | 0x00800000 FIXME!
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NextValue(self.m1, Cat(self.fs1[16:23], 1, 0, 0,0,0)), # | 0x00800000
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#NextValue(self.m2, Cat(self.fs2[0:23], 1, 0)), # | 0x00800000
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NextValue(self.m2, Cat(self.fs2[0:7], 1, 0, 0,0,0)), # | 0x00800000
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#NextValue(self.m2, Cat(self.fs2[0:7], 1, 0, 0,0,0)), # | 0x00800000 FIXME!
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NextValue(self.m2, Cat(self.fs2[16:23], 1, 0, 0,0,0)), # | 0x00800000
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If(self.fdiv, # Division
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NextState("FDIV1"),
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).Elif(self.fmin, # Minimum
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@ -103,7 +108,8 @@ class bfloat16Processor(Module):
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NextValue(self.sign1, self.fs1[31]),
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NextValue(self.e1, self.fs1[23:31] - 127),
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#NextValue(self.m1, Cat(self.fs1[0:23], 1, 0)), # | 0x00800000
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NextValue(self.m1, Cat(self.fs1[0:7], 1, 0, 0,0,0)), # | 0x00800000
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#NextValue(self.m1, Cat(self.fs1[0:7], 1, 0, 0,0,0)), # | 0x00800000 FIXME!
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NextValue(self.m1, Cat(self.fs1[16:23], 1, 0, 0,0,0)), # | 0x00800000
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NextState("FSQRT1"),
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)
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)
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@ -141,7 +147,7 @@ class bfloat16Processor(Module):
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NextValue(self.fready, 1),
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NextState("FPU_IDLE")
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).Elif((self.fmadd | self.fmsub | self.fnmadd | self.fnmsub) & ((self.e2 == 0) & (self.m2 == 0)), # Nothing to add (w/o sign!)
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NextState("self.fresult") # Just supply (normalized finally!) result from multiplication!
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NextState("FRESULT") # Just supply (normalized finally!) result from multiplication!
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).Else( # Ok, valid floats supplied ...
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NextValue(self.s_bit, 0),
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NextValue(self.branch1, 0), # Reset helpers
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@ -236,7 +242,7 @@ class bfloat16Processor(Module):
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NextValue(self.m3, self.m3 + self.s_bit),
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NextState("FADD8") # Adjust possible overflow ...
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).Else( # Nope, all ready
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NextState("self.fresult")
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NextState("FRESULT")
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)
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)
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)
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@ -247,10 +253,10 @@ class bfloat16Processor(Module):
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NextValue(self.m3, self.m3 >> 1), # Adjust mantissa & increment exponent
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NextValue(self.e3, self.e3 + 1)
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),
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NextState("self.fresult")
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NextState("FRESULT")
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) # End of fadd.s processing
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FPU_fsm.act("self.fresult", # Result contruction & possible rounding
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FPU_fsm.act("FRESULT", # Result contruction & possible rounding
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NextValue(self.FPU_state, 9),
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# 6. Build the actual resulting float
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#NextValue(self.fresult, Cat(self.m3[0:23], self.e3+127, self.sign3)),
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@ -327,23 +333,33 @@ class bfloat16Processor(Module):
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# 6. Construction of result
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NextValue(self.m3, (self.lm3 >> 23) & 0x7FFFFF),
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# TODO: e3=se3 omitted ok?
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If(self.fmul, # Simple multiplication
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NextState("self.fresult")
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If(self.fmul, # Simple multiplication
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NextState("FRESULT")
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).Else( # Fused multiply-add?
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NextValue(self.sign3, self.sign3 ^ (self.fnmadd | self.fnmsub)), # Negate mult. result w/ f<n>xxx
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NextState("FMADD1")
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)
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) # End of fmul.s processing
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FPU_fsm.act("FMADD1",
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FPU_fsm.act("FMADD1",
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# sign3/e3/m3 -> sign1/e1/m1, fs3 -> sign2/e2/m2
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NextValue(self.sign1, self.sign3), # Negate mult. result w/ f<n>xxx
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NextValue(self.sign2, self.fs3[31] ^ (self.fmsub | self.fnmsub)), # Invert sign for subtraction!
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NextValue(self.e1, self.e3),
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NextValue(self.e2, self.fs3[23:31] - 127),
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#NextValue(self.m1, Cat(0,0,0, self.m3[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
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NextValue(self.m1, Cat(0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, self.m3[0:7], 1, 0)), # | 0x00800000 + R/G/S bits
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#NextValue(self.m1, Cat(0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, self.m3[0:7], 1, 0)), # | 0x00800000 + R/G/S bits
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NextValue(self.m1, Cat(0,0,0, self.m3[0:7], 1, 0)), # | 0x00800000 + R/G/S bits
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#NextValue(self.m2, Cat(0,0,0, self.fs3[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
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NextValue(self.m2, Cat(0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, self.fs3[0:7], 1, 0)), # | 0x00800000 + R/G/S bits
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NextState("FADD1")
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#NextValue(self.m2, Cat(0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, self.fs3[16:23], 1, 0)), # | 0x00800000 + R/G/S bits
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NextValue(self.m2, Cat(0,0,0, self.fs3[16:23], 1, 0)), # | 0x00800000 + R/G/S bits
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# sign3/e3/m3 -> fs1 (reconstruction, nec. for compares, s.a.!)
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NextValue(self.fs1, Cat(0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, self.m3[0:7], (self.e3+127)[0:8], self.sign3)),
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# fs3 -> fs2
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NextValue(self.fs2, self.fs3),
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NextState("FADD1") # Add fs1 & fs2!
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)
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FPU_fsm.act("FDIV1",
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@ -397,7 +413,7 @@ class bfloat16Processor(Module):
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NextValue(self.m3, self.m3 << 1), # Subtraction normalization
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NextValue(self.e3, self.e3 - 1),
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).Else(
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NextState("self.fresult")
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NextState("FRESULT")
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)
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)
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) # End of fdiv.s processing
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