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An RV32IMF implementation w/ migen/LiteX
79 Commits
1 Branch
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2.5 MiB
Python 63.6%
C 34.2%
Shell 2.2%
 
 
 
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kaqu 9676712e54 ROM avail. w/ bus not accessible?! Interrupts miss 2021-02-25 12:46:19 +01:00
.vscode DMA transfer (s/w) version running first time 2020-12-26 18:03:20 +01:00
debugger Compiles but fails after load! 2021-02-18 19:19:04 +01:00
firmware Compiling (yet not working ...) 2020-12-23 12:57:44 +01:00
helpers Compiles but fails after load! 2021-02-18 19:19:04 +01:00
impress presentation updates, working (almost complete!) 2021-02-10 11:33:16 +01:00
libmodules CSR regs access read fails (& write?), random ... 2021-02-16 12:36:25 +01:00
litex ROM avail. w/ bus not accessible?! Interrupts miss 2021-02-25 12:46:19 +01:00
prog Started w/ DRAM access tests ... 2020-12-21 10:54:53 +01:00
software Compiles but fails after load! 2021-02-18 19:19:04 +01:00
.gitignore Debugger separated 2021-01-21 18:43:58 +01:00
risq5_wo_vex.py ROM avail. w/ bus not accessible?! Interrupts miss 2021-02-25 12:46:19 +01:00