An RV32IMF implementation w/ migen/LiteX
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kaqu 9676712e54 ROM avail. w/ bus not accessible?! Interrupts miss 2 years ago
.vscode DMA transfer (s/w) version running first time 2 years ago
debugger Compiles but fails after load! 2 years ago
firmware Compiling (yet not working ...) 2 years ago
helpers Compiles but fails after load! 2 years ago
impress presentation updates, working (almost complete!) 2 years ago
libmodules CSR regs access read fails (& write?), random ... 2 years ago
litex ROM avail. w/ bus not accessible?! Interrupts miss 2 years ago
prog Started w/ DRAM access tests ... 2 years ago
software Compiles but fails after load! 2 years ago
.gitignore Debugger separated 2 years ago
risq5_wo_vex.py ROM avail. w/ bus not accessible?! Interrupts miss 2 years ago