An RV32IMF implementation w/ migen/LiteX
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kaqu 01818b44a4 Fixed zero operand problems (hopefully!) 9 months ago
.. Brushup for publication ... 9 months ago fcnvt.w.s bug in 0..1 range 10 months ago Not getting lost on fast L1 reloads now ... (mret) 12 months ago Fixed zero operand problems (hopefully!) 9 months ago rs1 bit width for csrs now ok! 10 months ago fcsr/fflags/frm csr reg. handling started ... 10 months ago fsflagsi still defective ... 10 months ago Register need returns (cached?) old values ... 12 months ago


File contents: - contains main helpers for DRAM access. - contains the FPU instruction decoder for most 'F' extension opcodes.
A note on the square root logic: I have implemented a variant of Goldschmidt's algorithm which allows for up to ⚠ 3.5% error, but there is simply no replacement for speed! If you need more accuracy, you will have to implement Newton-Raphson in s/w or perhaps doubles w/ external lib. calls. Example:

    // Newton-Raphson approximation (6 digits after decimal ok)        
    #define MAXITERATION 128
    #define ACCURRACY 1E-16

    float f = <value>; // Whatever you wanna calc.!
    float approx = 0.5 * f; // 1st approximation
    float betterapprox;            
    for(int i=0;i < MAXITERATION;i++) {
        betterapprox = 0.5 * (approx + f/approx);                
        if(f_abs(betterapprox - approx) < ACCURRACY)
        approx = betterapprox;        
    } - contains the main instruction decoder für base 'I', multiply/divide 'M' & a few 'F' extension opcodes. - contains the register file implementation, opcode dissection & some combinatorial adressing logic. - contains the definitions for the nec. control & status registers (CSRs) as well as some exception codes. - contains a memory mapped clock as required according to RISC-V spec.