An RV32IMF implementation w/ migen/LiteX
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kaqu 01818b44a4 Fixed zero operand problems (hopefully!) 9 months ago
..
README.md Brushup for publication ... 9 months ago
core.py fcnvt.w.s bug in 0..1 range 10 months ago
dramtransfer.py Not getting lost on fast L1 reloads now ... (mret) 12 months ago
fpu_decode.py Fixed zero operand problems (hopefully!) 9 months ago
instruction_decode.py rs1 bit width for csrs now ok! 10 months ago
register_file.py fcsr/fflags/frm csr reg. handling started ... 10 months ago
risq5defs.py fsflagsi still defective ... 10 months ago
systime.py Register need returns (cached?) old values ... 12 months ago

README.md

LIBMODULES

File contents:

dramtransfer.py - contains main helpers for DRAM access.

fpu_decode.py - contains the FPU instruction decoder for most 'F' extension opcodes.
A note on the square root logic: I have implemented a variant of Goldschmidt's algorithm which allows for up to ⚠ 3.5% error, but there is simply no replacement for speed! If you need more accuracy, you will have to implement Newton-Raphson in s/w or perhaps doubles w/ external lib. calls. Example:

    // Newton-Raphson approximation (6 digits after decimal ok)        
    #define MAXITERATION 128
    #define ACCURRACY 1E-16

    float f = <value>; // Whatever you wanna calc.!
    float approx = 0.5 * f; // 1st approximation
    float betterapprox;            
    for(int i=0;i < MAXITERATION;i++) {
        betterapprox = 0.5 * (approx + f/approx);                
        if(f_abs(betterapprox - approx) < ACCURRACY)
            break;    
        approx = betterapprox;        
    }

instruction_decode.py - contains the main instruction decoder für base 'I', multiply/divide 'M' & a few 'F' extension opcodes.

register_file.py - contains the register file implementation, opcode dissection & some combinatorial adressing logic.

risq5defs.py - contains the definitions for the nec. control & status registers (CSRs) as well as some exception codes.

systime.py - contains a memory mapped clock as required according to RISC-V spec.