kaqu
|
4f15e12168
|
M extension started, mulhsu sign wrong?
|
2 years ago |
|
kaqu
|
5ba92370ba
|
CSR regs access read fails (& write?), random ...
|
2 years ago |
|
kaqu
|
956d07c49d
|
Register need returns (cached?) old values ...
|
2 years ago |
|
kaqu
|
28e696bff3
|
Invalid instruction detect corrected
|
2 years ago |
|
kaqu
|
961f0194c7
|
Interrupt execution full speed ok!
|
2 years ago |
|
kaqu
|
80d963bb89
|
Cache flooding error?!
|
2 years ago |
|
kaqu
|
beb5686951
|
Timing optimized (not ok yet)
|
2 years ago |
|
kaqu
|
550dc9ceb6
|
Resetless signals, streamlined
|
2 years ago |
|
kaqu
|
1425cb42a7
|
CSRs as Array (>gen. time!)
|
2 years ago |
|
kaqu
|
6c80762ad8
|
CSRs integrated (though w/o special functions)
|
2 years ago |
|
kaqu
|
6cbe1661b2
|
1st pass opcodes thru!
|
2 years ago |
|
kaqu
|
0c48cf622f
|
'til sltu included
|
2 years ago |
|
kaqu
|
42310114de
|
sb, sh added
|
2 years ago |
|
kaqu
|
89ee95ce06
|
not sb yet ...
|
2 years ago |
|
kaqu
|
eaf49fc34e
|
jalr target ok, cache helper ok
|
2 years ago |
|
kaqu
|
59455f01f4
|
jalr added (boundaries unverified, not caching)
|
2 years ago |
|
kaqu
|
27bcdc51cc
|
jal added
|
2 years ago |
|
kaqu
|
53852660df
|
95% full, til ecall (1st pass)
|
2 years ago |
|
kaqu
|
3afa889725
|
SUUnit working!
|
2 years ago |
|
kaqu
|
b85b3035e8
|
L1 load via debugger fails?!
|
2 years ago |
|
kaqu
|
134d9dfe9f
|
Load unit & register transfer ok (finally!)
|
2 years ago |
|
kaqu
|
8460512a19
|
Load unit works, opcodes write 2 regs?!
|
2 years ago |
|
kaqu
|
72eb2eea90
|
branch cache boundaries verified
|
2 years ago |
|
kaqu
|
8d4ca99bcb
|
Cache reload on branches ok, compare fails
|
2 years ago |
|
kaqu
|
3bfbb7979b
|
branch calc ok, cache not :-(
|
2 years ago |
|
kaqu
|
64412d6e8d
|
add working!
|
2 years ago |
|
kaqu
|
fcb2580475
|
Seems to work? Internal bug circumvented ... (?!)
|
2 years ago |
|
kaqu
|
33272bced1
|
faulty decode integration
|
2 years ago |
