Permit ROM/BIOS integration w/o CPU argument

master
kaqu 2 years ago
parent e9723a6d61
commit fb96c34d61
  1. 3
      .vscode/launch.json
  2. 18
      litex/litex/soc/integration/builder.py
  3. 6
      litex/litex/soc/integration/soc_core.py
  4. 11
      risq5_wo_vex.py

@ -18,7 +18,8 @@
"--with-etherbone",
"--ip-address=192.168.1.20",
"--csr-csv=build/csr.csv", // Only this one for remotetest.py!
"--doc"
"--doc" // Generate documentation files for sphinx
//"--with-bios-for-none" // Provide ROM & BIOS even w/o CPU (+10 minutes!)
],
//"args": ["--build"],
//"pythonArgs": ["--build", "--uart-name=crossover"],

@ -61,8 +61,9 @@ class Builder:
csr_json = None,
csr_csv = None,
csr_svd = None,
memory_x = None,
bios_options = []):
memory_x = None,
bios_options = [],
with_bios_for_none = False):
self.soc = soc
# From Python doc: makedirs() will become confused if the path elements to create include '..'
@ -276,12 +277,13 @@ class Builder:
if self.soc.integrated_rom_size and self.compile_software:
if not self.soc.integrated_rom_initialized:
self._initialize_rom_software()
else: # 24.02.21/KQ Added (we want a BIOS w/o internal cpu!)
self._prepare_rom_software()
self._generate_rom_software(not self.soc.integrated_rom_initialized)
if self.soc.integrated_rom_size and self.compile_software:
if not self.soc.integrated_rom_initialized:
self._initialize_rom_software()
else: # 24.02.21/KQ Added (we want a BIOS w/o internal cpu!)
if self.compile_software:
self._prepare_rom_software()
self._generate_rom_software(not self.soc.integrated_rom_initialized)
if self.soc.integrated_rom_size and self.compile_software:
if not self.soc.integrated_rom_initialized:
self._initialize_rom_software()
if "run" not in kwargs:
kwargs["run"] = self.compile_gateware

@ -97,6 +97,8 @@ class SoCCore(LiteXSoC):
timer_uptime = False,
# Controller parameters
with_ctrl = True,
# BIOS w/ cpu None
with_bios_for_none = False, # 26.02.21/KQ Added
# Others
**kwargs):
@ -116,6 +118,8 @@ class SoCCore(LiteXSoC):
irq_n_irqs = 32,
irq_reserved_irqs = {},
#with_bios_for_none = False, # 26.02.21/KQ Added
)
# Attributes
@ -134,7 +138,7 @@ class SoCCore(LiteXSoC):
# 25.02.21/KQ Removed: if cpu_type in [None, "zynq7000"]:
# TODO: w/o bios -> reverse! Saves 10 minutes translation time!
if cpu_type in ["zynq7000"]:
if (cpu_type in ["zynq7000"]) or ((cpu_type in [None]) and (not with_bios_for_none)):
integrated_rom_size = 0 # Otherwise: remains 32Kb
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []

@ -125,7 +125,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
def __init__(self, board, revision, with_ethernet=False, with_etherbone=False, eth_phy=0, ip_address=None, mac_address=None, sys_clk_freq=60e6, use_internal_osc=False, sdram_rate="1:1", **kwargs):
def __init__(self, board, revision, with_ethernet=False, with_etherbone=False, eth_phy=0, ip_address=None, mac_address=None, sys_clk_freq=60e6, use_internal_osc=False, sdram_rate="1:1", with_bios_for_none=False, **kwargs):
platform = colorlight_5a_75b.Platform(revision="7.0")
# SoCCore ----------------------------------------------------------------------------------
@ -133,6 +133,7 @@ class BaseSoC(SoCCore):
SoCCore.__init__(self, platform, int(sys_clk_freq),
ident = "LiteX SoC on Colorlight " + board.upper(),
ident_version = True,
with_bios_for_none = with_bios_for_none,
**kwargs)
# CRG --------------------------------------------------------------------------------------
@ -280,10 +281,11 @@ def main():
parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
parser.add_argument("--csr_csv", default="build/csr.csv", help="CSR list location")
parser.add_argument("--doc", action="store_true", help="Create doc files for sphinx generator")
parser.add_argument("--with-bios-for-none", action="store_true", help="Create ROM w/ BIOS even w/o CPU")
parser.add_argument("--flash", action="store_true", help="Load bitstream to flash")
args = parser.parse_args()
#assert not (args.with_ethernet and args.with_etherbone)
#assert not (args.with_ethernet and args.with_etherbone)
soc = BaseSoC(board=args.board, revision=args.revision,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
@ -292,7 +294,7 @@ def main():
mac_address = int(args.mac_address, 0),
sys_clk_freq = args.sys_clk_freq,
use_internal_osc = args.use_internal_osc,
sdram_rate = args.sdram_rate,
sdram_rate = args.sdram_rate,
**soc_core_argdict(args))
# 32MBit SPIFlash ------------------------------------------------------------------------
@ -306,6 +308,9 @@ def main():
builder = Builder(soc, **builder_argdict(args))
# Now override boot address (used to be zero/default)
args.ecppack_bootaddr = flashbase + flashoffset # 0xC0100000
if not args.with_bios_for_none: # 26.02.21/KQ Added
builder.compile_software = False # Cut off BIOS integration
builder.build(**trellis_argdict(args), run=args.build) # Written here to (local) build tree
if args.doc:

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