Permit ROM/BIOS integration w/o CPU argument
kaqu
parent
e9723a6d61
commit
fb96c34d61
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@ -18,7 +18,8 @@
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"--with-etherbone",
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"--ip-address=192.168.1.20",
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"--csr-csv=build/csr.csv", // Only this one for remotetest.py!
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"--doc"
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"--doc" // Generate documentation files for sphinx
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//"--with-bios-for-none" // Provide ROM & BIOS even w/o CPU (+10 minutes!)
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],
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//"args": ["--build"],
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//"pythonArgs": ["--build", "--uart-name=crossover"],
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@ -61,8 +61,9 @@ class Builder:
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csr_json = None,
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csr_csv = None,
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csr_svd = None,
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memory_x = None,
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bios_options = []):
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memory_x = None,
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bios_options = [],
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with_bios_for_none = False):
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self.soc = soc
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# From Python doc: makedirs() will become confused if the path elements to create include '..'
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@ -276,12 +277,13 @@ class Builder:
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if self.soc.integrated_rom_size and self.compile_software:
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if not self.soc.integrated_rom_initialized:
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self._initialize_rom_software()
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else: # 24.02.21/KQ Added (we want a BIOS w/o internal cpu!)
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self._prepare_rom_software()
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self._generate_rom_software(not self.soc.integrated_rom_initialized)
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if self.soc.integrated_rom_size and self.compile_software:
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if not self.soc.integrated_rom_initialized:
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self._initialize_rom_software()
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else: # 24.02.21/KQ Added (we want a BIOS w/o internal cpu!)
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if self.compile_software:
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self._prepare_rom_software()
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self._generate_rom_software(not self.soc.integrated_rom_initialized)
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if self.soc.integrated_rom_size and self.compile_software:
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if not self.soc.integrated_rom_initialized:
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self._initialize_rom_software()
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if "run" not in kwargs:
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kwargs["run"] = self.compile_gateware
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@ -97,6 +97,8 @@ class SoCCore(LiteXSoC):
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timer_uptime = False,
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# Controller parameters
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with_ctrl = True,
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# BIOS w/ cpu None
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with_bios_for_none = False, # 26.02.21/KQ Added
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# Others
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**kwargs):
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@ -116,6 +118,8 @@ class SoCCore(LiteXSoC):
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irq_n_irqs = 32,
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irq_reserved_irqs = {},
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#with_bios_for_none = False, # 26.02.21/KQ Added
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)
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# Attributes
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@ -134,7 +138,7 @@ class SoCCore(LiteXSoC):
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# 25.02.21/KQ Removed: if cpu_type in [None, "zynq7000"]:
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# TODO: w/o bios -> reverse! Saves 10 minutes translation time!
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if cpu_type in ["zynq7000"]:
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if (cpu_type in ["zynq7000"]) or ((cpu_type in [None]) and (not with_bios_for_none)):
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integrated_rom_size = 0 # Otherwise: remains 32Kb
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self.integrated_rom_size = integrated_rom_size
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self.integrated_rom_initialized = integrated_rom_init != []
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@ -125,7 +125,7 @@ class _CRG(Module):
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, board, revision, with_ethernet=False, with_etherbone=False, eth_phy=0, ip_address=None, mac_address=None, sys_clk_freq=60e6, use_internal_osc=False, sdram_rate="1:1", **kwargs):
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def __init__(self, board, revision, with_ethernet=False, with_etherbone=False, eth_phy=0, ip_address=None, mac_address=None, sys_clk_freq=60e6, use_internal_osc=False, sdram_rate="1:1", with_bios_for_none=False, **kwargs):
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platform = colorlight_5a_75b.Platform(revision="7.0")
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# SoCCore ----------------------------------------------------------------------------------
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@ -133,6 +133,7 @@ class BaseSoC(SoCCore):
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SoCCore.__init__(self, platform, int(sys_clk_freq),
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ident = "LiteX SoC on Colorlight " + board.upper(),
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ident_version = True,
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with_bios_for_none = with_bios_for_none,
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**kwargs)
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# CRG --------------------------------------------------------------------------------------
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@ -280,10 +281,11 @@ def main():
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parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
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parser.add_argument("--csr_csv", default="build/csr.csv", help="CSR list location")
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parser.add_argument("--doc", action="store_true", help="Create doc files for sphinx generator")
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parser.add_argument("--with-bios-for-none", action="store_true", help="Create ROM w/ BIOS even w/o CPU")
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parser.add_argument("--flash", action="store_true", help="Load bitstream to flash")
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args = parser.parse_args()
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#assert not (args.with_ethernet and args.with_etherbone)
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#assert not (args.with_ethernet and args.with_etherbone)
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soc = BaseSoC(board=args.board, revision=args.revision,
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with_ethernet = args.with_ethernet,
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with_etherbone = args.with_etherbone,
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@ -292,7 +294,7 @@ def main():
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mac_address = int(args.mac_address, 0),
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sys_clk_freq = args.sys_clk_freq,
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use_internal_osc = args.use_internal_osc,
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sdram_rate = args.sdram_rate,
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sdram_rate = args.sdram_rate,
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**soc_core_argdict(args))
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# 32MBit SPIFlash ------------------------------------------------------------------------
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@ -306,6 +308,9 @@ def main():
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builder = Builder(soc, **builder_argdict(args))
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# Now override boot address (used to be zero/default)
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args.ecppack_bootaddr = flashbase + flashoffset # 0xC0100000
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if not args.with_bios_for_none: # 26.02.21/KQ Added
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builder.compile_software = False # Cut off BIOS integration
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builder.build(**trellis_argdict(args), run=args.build) # Written here to (local) build tree
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if args.doc:
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