4 register variant up ...

master
kaqu 2 years ago
parent 9cdfa9edba
commit f4c5ba0fae
  1. 12
      debugger/dbgeval.py
  2. 20
      debugger/qt5dbg.py
  3. 6
      debugger/risq5dbg.py
  4. 18
      libmodules/instruction_decode.py
  5. 26
      libmodules/register_file.py
  6. 24
      software/source/flwstw.c

@ -221,10 +221,18 @@ def disassemble(opcode, pc):
msg = "fence.i (ignored)"
else:
msg = "fence {0} (ignored)".format(hex(opcode))
elif op == 0x07:
elif op == 0x07: # F-Extension
msg = "flw {0},{1}({2})".format(f_description[rd], hex(imm_i), x_description[rs1])
elif op == 0x27:
elif op == 0x27: # F-Extension
msg = "fsw {0},{1}({2})".format(f_description[rs2], hex(imm_s), x_description[rs1])
elif op == 0x53: # R-Type (F-Extension)
if f7 == 0x70:
if f3 == 0x00:
msg = "fmv.x.s {0},{1}".format(x_description[rd], f_description[rs1])
else:
msg = "fclass.s"
else: # Last operation for op==0x53 ...
msg = "fmv.s.x {0},{1}".format(f_description[rd], x_description[rs1])
else:
msg = "-- illegal? --"
print("Illegal opcode detected: {0} @{1}?".format(hex(opcode),hex(pc)))

@ -8,7 +8,7 @@ Pandemic Pong view client only
"""
import sys, time
import sys, time, struct
from functools import partial
from PyQt5.QtGui import QPixmap
@ -321,9 +321,10 @@ class dbgWindow(QMainWindow):
for i in range(self.MAXLABEL): # Walk f<n> register file
self.wb.regs.risq5ext_b5_wb_reg_no.write(i) # Select register
val = self.wb.regs.risq5ext_b32_wb_freg_value_r.read() # Pick actual register risq5_b32_wb_reg_value_r
val = val # Translate hex value -> decimal float!
self.txtFList[i].setText("0x{:08X}".format(val))
p = struct.pack("I",val) # Translate 32-bit value -> decimal float!
dz = struct.unpack("f", p)
self.txtFList[i].setText("{:6f}".format(dz[0]))
pc = self.wb.regs.risq5ext_b32_PC.read()
self.txtPC.setText("0x{:08X}".format(pc))
opcode = self.wb.regs.risq5ext_b32_opcode.read()
@ -372,14 +373,17 @@ class dbgWindow(QMainWindow):
self.timer.stop() # Block interference
sender = self.sender() # Where are we coming from?
try:
# TODO: Translate decimal to hex value 1st!
b32Value = int(sender.text(),16) # Get hex value
#print("x{0} new value: {1}".format(index, b32Value))
# TODO: Translate decimal to binary value 1st!
fval = float(sender.text()) # Get hex value
dz = struct.pack("f", fval)
b32Value = struct.unpack("I", dz)
print("f{0} new value: {1} (0x{2:08X})".format(index, fval, b32Value[0]))
self.wb.regs.risq5ext_b5_wb_reg_no.write(index) # Write index
self.wb.regs.risq5ext_b32_wb_reg_value_w.write(b32Value) # New value
self.wb.regs.risq5ext_b32_wb_reg_value_w.write(b32Value[0]) # New value
self.wb.regs.risq5ext_b1_wb_freg_we.write(1) # Write float request (pulse)
time.sleep(0.05) # Just make sure ...
except:
print("returnFPressed(): conversion fault?!")
pass
self.wb.regs.risq5ext_b1_wb_freg_we.write(0) # Write request (pulse)
self.qpbUpdate.setVisible(False)

@ -57,9 +57,9 @@ def main():
parser.add_argument("--doc", action="store_true", help="not used")
parser.add_argument("--flash", action="store_true", help="not used")
parser.add_argument("--uart-name", default="crossover", help="not used")
parser.add_argument("--isa-extension-m", action="store_true", help="RISC-V extension M")
parser.add_argument("--isa-extension-f", action="store_true", help="RISC-V extension F")
parser.add_argument("--with-bios-for-none", action="store_true", help="Create ROM w/ BIOS even w/o CPU")
parser.add_argument("--isa-extension-m", action="store_true", help="not used")
parser.add_argument("--isa-extension-f", action="store_true", help="not used")
parser.add_argument("--with-bios-for-none", action="store_true", help="not used")
args = parser.parse_args()
risq5dbg(args.csr_csv) # Point of no return ...

@ -306,7 +306,7 @@ class Risq5Decoder(Module):
NextValue(self.LUReload, 1), # Enforce cache reload (for now: allways! TODO: Separate?)
).Elif(regs.op == 0x27, # S-Type: fsw frs2, imm_offset(xs1)
NextValue(SU_Unit.b32Address.storage, regs.xs1u + regs.imm_s), # Adjust DRAM target address
NextValue(SU_Unit.bData, regs.frs2), # Pick actual value to store (from fs2) & load SU
NextValue(SU_Unit.bData, regs.fs2), # Pick actual value to store (from fs2) & load SU
NextValue(self.SUByteID, 7), # Type: Word (6->7!)
NextValue(self.SUStore, 1), # Enforce store unit engagement (for now: allways!)
).Elif(regs.op == 0x43, # R4-Type: fmadd.s
@ -349,8 +349,9 @@ class Risq5Decoder(Module):
NextValue(self.DECODE_state, 0x0F), # Dummy action
)
).Elif(regs.f7 == 0x70, # fmv/fclass
If(regs.f3 == 0x00, # fmv.x.w
NextValue(self.DECODE_state, 0x0F), # Dummy action
If(regs.f3 == 0x00, # fmv.x.s rd, frs1 (f-reg -> x-reg)
NextValue(regs.rd_wrport.dat_w, regs.fs1),
NextValue(self.write, 1), # Trigger write rd (x-reg)
).Else( #regs.f3 == 0x01, # fclass.s
NextValue(self.DECODE_state, 0x0F), # Dummy action
)
@ -368,8 +369,9 @@ class Risq5Decoder(Module):
).Else( #regs.rs2 == 0x01, # fcvt.s.wu
NextValue(self.DECODE_state, 0x0F), # Dummy action
)
).Else( # regs.f7 == 0x78, # fmv.w.x
NextValue(self.DECODE_state, 0x0F), # Dummy action
).Else( # regs.f7 == 0x78, # fmv.s.x frd, rs1 (x-reg -> f-reg)
NextValue(regs.frd_wrport.dat_w, regs.xs1u),
NextValue(self.fwrite, 1), # Trigger write frd (f-reg)
)
# TODO: Maybe RISC-V extensions ...
@ -513,7 +515,11 @@ class Risq5Decoder(Module):
NextValue(regs.rd_wrport.dat_w, LUCache.b32Data.storage[16:32] | 0xFFFF0000), # Load byte sign-extended
)
),
NextValue(self.write, 1), # Indicate WRITE (rd) validity (now ready!)
If(regs.op == 0x07, # F-Extension: flw ->frd
NextValue(self.fwrite, 1)
).Else( # lb/lh/lw ->rd
NextValue(self.write, 1), # Indicate WRITE (rd) validity (now ready!)
),
NextState("DECODE_WRITE") # Load delay for opcode cache is next
)
).Else( # Time not yet elapsed ...

@ -45,10 +45,10 @@ class Risq5RegisterFile(Module):
self.comb += [ # Opcode relay
# Common parts
self.op.eq(self.opcode[0:7]),
self.rd.eq(self.opcode[7:12]),
self.rd.eq(self.opcode[7:12]),
self.f3.eq(self.opcode[12:15]),
self.rs1.eq(self.opcode[15:20]),
self.rs2.eq(self.opcode[20:25]),
self.rs1.eq(self.opcode[15:20]),
self.rs2.eq(self.opcode[20:25]),
# R-type
self.f7.eq(self.opcode[25:32]),
# I-type immediate (12 bits)
@ -73,7 +73,10 @@ class Risq5RegisterFile(Module):
self.xs2u = Signal(32, reset_less=True) # Value of source register #2 (unsigned)
self.xs1s = Signal((32,True), reset_less=True) # Signed register #1
self.xs2s = Signal((32,True), reset_less=True) # Signed register #2
self.fs1 = Signal(32, reset_less=True) # F-Extension: Float register #1
self.fs2 = Signal(32, reset_less=True) # F-Extension: Float register #2
self.fs3 = Signal(32, reset_less=True) # F-Extension: Float register #3
self.rd_mul64u = Signal(64, reset_less=True) # M extension multiply result (unsigned)
self.rd_mul64s = Signal((64,True), reset_less=True) # M extension multiply result (signed)
self.rd_mul64su = Signal((64,True), reset_less=True) # M extension multiply result (signed x unsigned)
@ -126,13 +129,20 @@ class Risq5RegisterFile(Module):
# Risq5 floating point unit (FPU extension)
# Instruction decode, 32 bit opcode parts --------------------------------------------------
self.frd = Signal(CPUREGADDRESSBITS, reset_less=True) # [11:7] Destination register
#self.rm = Signal(3, reset_less=True) # [14:12] Instruction type modifier
#self.rm = Signal(3, reset_less=True) # [14:12] Instruction type modifier
self.frs1 = Signal(CPUREGADDRESSBITS, reset_less=True) # [19:15] source register #1
self.frs2 = Signal(CPUREGADDRESSBITS, reset_less=True) # [24:20] source register #2
self.frs3 = Signal(CPUREGADDRESSBITS, reset_less=True) # [31:27] Instruction type modifier
self.fread_ext_index = Signal(CPUREGADDRESSBITS, reset_less=True) # External read access (index)
self.fwrite_ext_index = Signal(CPUREGADDRESSBITS, reset_less=True) # External write access (index)
self.comb += [ # Opcode relay: f-reg adressing
self.frd.eq(self.opcode[7:12]), # Write f-reg pointer
self.frs1.eq(self.opcode[15:20]), # Read f-reg pointer
self.frs2.eq(self.opcode[20:25]),
self.frs3.eq(self.opcode[27:32])
]
fregs = Memory(WORDSIZE, CPUREGS) #32) # 32-bit, 32 elements -> f0 .. f31
self.specials += fregs
# rd -> index register to write
@ -159,11 +169,11 @@ class Risq5RegisterFile(Module):
self.specials += fext_rdport
self.comb += [ # Read from memory
frs1_rdport.adr.eq(self.frs1), # Read source register #1
self.frs1.eq(frs1_rdport.dat_r),
self.fs1.eq(frs1_rdport.dat_r),
frs2_rdport.adr.eq(self.frs2), # Read source register #2
self.frs2.eq(frs2_rdport.dat_r),
self.fs2.eq(frs2_rdport.dat_r),
frs3_rdport.adr.eq(self.frs3), # Read source register #3
self.frs3.eq(frs3_rdport.dat_r),
self.fs3.eq(frs3_rdport.dat_r),
fext_rdport.adr.eq(self.fread_ext_index), # Read from external
self.ext_f.eq(fext_rdport.dat_r),
]

@ -5,10 +5,32 @@ static void start(void)
auipc ra,0 # Store current pc \n\
lui sp,%hi(0x40192000) # Setup stack pointer \n\
addi sp,sp,%lo(0x40192000) # s.a. \n\
li x3, 123 # Load \n\
lw x3,0(sp) # Load float from stack (test) \n\
lw x3,4(sp) # Load float from stack (test) \n\
lui x3, %hi(0x01040000) # Load \n\
fmv.x.s x3,f0 # f0 -> x3 \n\
fmv.s.x f0,x3 # x3 -> f0 \n\
sw x3,0(sp) # Save to stack \n\
flw f0,0(sp) # Load float from stack \n\
nop # ... \n\
fsw f0,4(sp) # Store float on stack \n\
nop # ... \n\
lui x3,%hi(0x12345678) # Load template value \n\
addi x3,x3,%lo(0x12345678) # lo & hi \n\
fmv.s.x f1,x3 # x3 -> f1 \n\
nop # \n\
fsw f1,0(sp) \n\
addi x3,x3,1 \n\
fsw f1,4(sp) \n\
addi x3,x3,1 \n\
fsw f1,8(sp) \n\
addi x3,x3,1 \n\
fsw f1,12(sp)\n\
nop \n\
lw x3,0(sp) \n\
lw x3,4(sp) \n\
lw x3,8(sp) \n\
lw x3,12(sp) \n\
");
#include "onek_nops.c"

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