IRQ (dummies) now avail. as well ...

litex/litex/soc/integration/builder.py

@@ -263,13 +263,12 @@ class Builder:
         os.makedirs(self.gateware_dir, exist_ok=True)
         os.makedirs(self.software_dir, exist_ok=True)
 
-        self.soc.finalize()
-        #assert(False)
+        self.soc.finalize()        
         
         self._generate_includes()
         self._generate_csr_map()
-        self._generate_mem_region_map()
-    
+        self._generate_mem_region_map()        
+
         if self.soc.cpu_type is not None:
             if self.soc.cpu.use_rom: 
                 self._prepare_rom_software()

litex/litex/soc/integration/soc.py

@@ -866,11 +866,12 @@ class SoC(Module):
             if reset_address is None:
                 reset_address = self.mem_map["rom"]
             self.cpu.set_reset_address(reset_address)
-            # TODO: 18.02.21/KQ No peripheral bus for now
-            #for n, cpu_bus in enumerate(self.cpu.periph_buses):
-            #    self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus)
-            #assert(False)
+            # FIXME 18.02.21/KQ No peripheral bus for Risq5
+            for n, cpu_bus in enumerate(self.cpu.periph_buses):
+                self.bus.add_master(name="cpu_bus{}".format(n), master=cpu_bus)
+
             self.csr.add("cpu", use_loc_if_exists=True)
+
             if hasattr(self.cpu, "interrupt"):
                 for name, loc in self.cpu.interrupts.items():
                     self.irq.add(name, loc)
@@ -893,6 +894,28 @@ class SoC(Module):
                 if hasattr(self.ctrl, "reset"):
                     self.comb += self.cpu.reset.eq(self.ctrl.reset)
             self.add_config("CPU_RESET_ADDR", reset_address)
+        elif isinstance(self.cpu, cpu.CPUNone): # 25.02.21/KQ Added            
+            """
+            # Adjust reset if nec.
+            #if reset_address is None:
+            #    reset_address = self.mem_map["rom"]
+            #self.cpu.set_reset_address(reset_address)
+            """
+            self.cpu.interrupt = Signal(32)
+            """
+            # Create optional DMA Bus (for Cache Coherence)
+            if hasattr(self.cpu, "dma_bus"):
+                self.submodules.dma_bus = SoCBusHandler(
+                    name             = "SoCDMABusHandler",
+                    standard         = "wishbone",
+                    data_width       = self.bus.data_width,
+                    address_width    = self.bus.address_width,
+                )
+                dma_bus = wishbone.Interface(data_width=self.bus.data_width)
+                self.dma_bus.add_slave("dma", slave=dma_bus, region=SoCRegion(origin=0x00000000, size=0x100000000)) # FIXME: covers lower 4GB only
+                self.submodules += wishbone.Converter(dma_bus, self.cpu.dma_bus)
+            """
+
         # Add constants
         self.add_config("CPU_TYPE",    str(name))
         self.add_config("CPU_VARIANT", str(variant.split('+')[0]))