0 result normalization error fixed, 0 fadd fixed

master
kaqu 2 years ago
parent 372802ffd3
commit e943825990
  1. 18
      libmodules/fpu_decode.py
  2. 1
      libmodules/instruction_decode.py

@ -102,7 +102,7 @@ class Risq5FPUDecoder(Module):
NextState("FPU_IDLE")
).Elif(regs.fs1[0:31] == 0, # Nothing to add? (w/o sign!)
If(self.fsub, # Subtract yields negative result!
NextValue(regs.frd_wrport.dat_w, -regs.fs2), # Ready!
NextValue(regs.frd_wrport.dat_w, regs.fs2 ^ 0x80000000), # Invert sign
).Else( # Straight add
NextValue(regs.frd_wrport.dat_w, regs.fs2), # Ready!
),
@ -121,20 +121,22 @@ class Risq5FPUDecoder(Module):
NextState("FADD2")
)
)
FPU_fsm.act("FADD2",
NextValue(self.FPU_state, 2),
FPU_fsm.act("FADD2",
# 2. Compare exponents: The higher one will be taken, the lower one adjusted
If(self.e1 < self.e2,
If(self.e1 < self.e2,
NextValue(self.FPU_state, 21),
If(self.m1[0], NextValue(self.s_bit, 1)), # Keep shifted out bits (ORed sticky bit)
NextValue(self.m1, self.m1 >> 1),
NextValue(self.e1, self.e1 + 1),
NextValue(self.branch1, 1),
).Elif(self.e1 > self.e2,
).Elif(self.e1 > self.e2,
NextValue(self.FPU_state, 22),
If(self.m2[0], NextValue(self.s_bit, 1)), # Keep shifted out bits (ORed sticky bit)
NextValue(self.m2, self.m2 >> 1),
NextValue(self.e2, self.e2 + 1),
NextValue(self.branch2, 1),
).Else(
NextValue(self.FPU_state, 23),
If(self.branch1, NextValue(self.m1, self.m1 | self.s_bit)), # Add sticky bit (if any)
If(self.branch2, NextValue(self.m2, self.m2 | self.s_bit)),
NextState("FADD3")
@ -188,15 +190,17 @@ class Risq5FPUDecoder(Module):
NextValue(self.m3, self.m3 >> 1), # Adjust mantissa & increment exponent
NextValue(self.e3, self.e3 + 1)
).Else(
NextValue(self.i, 0), # Reset for normalization restraining
NextState("FADD7")
)
)
FPU_fsm.act("FADD7",
# 7. Normalization: Result
NextValue(self.FPU_state, 7),
If(~self.m3[23], # & 0x00800000),
If(~self.m3[23] & (self.i < 23), # & 0x00800000 (limit to max. loops)
NextValue(self.m3, self.m3 << 1), # Subtraction normalization
NextValue(self.e3, self.e3 - 1)
NextValue(self.e3, self.e3 - 1),
NextValue(self.i, self.i + 1), # Count loops ...
).Else(
If(self.s_bit, # Do we need rounding?!
NextValue(self.m3, self.m3 + self.s_bit),

@ -623,6 +623,7 @@ class Risq5Decoder(Module):
)
# F-Extension: Wait for FPU ready signals
DECODE_fsm.act("FPU_WAIT",
NextValue(self.DECODE_state, fpu_decoder.FPU_state),
If(fpu_decoder.fready, # Wait for FPU decoder ready flag
NextValue(fpu_decoder.fadd, 0), # Reset job queue triggers (because of NFA reentry later!)
NextValue(fpu_decoder.fsub, 0),

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