fnmadd/fnmsub fixed -(full expr.)!

master
kaqu 1 year ago
parent 9b0f34a1c2
commit d5a8c95a34
  1. 16
      libmodules/fpu_decode.py

@ -158,9 +158,9 @@ class Risq5FPUDecoder(Module):
).Elif(regs.fs1[0:31] == 0, # Nothing to add? (w/o sign!)
If(self.fsub, # Subtract yields negative result!
NextValue(regs.frd_wrport.dat_w, regs.fs2 ^ 0x80000000), # Invert sign
).Elif(self.fmsub | self.fnmsub, # 0*x=>0! 0-fs3 = +fs3!
).Elif(self.fmsub | self.fnmadd, # 0*x=>0! 0-fs3 = -fs3!
NextValue(regs.frd_wrport.dat_w, regs.fs3 ^ 0x80000000), # Invert sign
).Elif(self.fmadd | self.fnmadd, # 0*x=>0! 0+fs3 = fs3!
).Elif(self.fmadd, # 0*x=>0! 0+fs3 = fs3!
NextValue(regs.frd_wrport.dat_w, regs.fs3), # Ready!
).Else( # Straight add
NextValue(regs.frd_wrport.dat_w, regs.fs2), # Ready!
@ -174,6 +174,9 @@ class Risq5FPUDecoder(Module):
NextValue(self.fready, 1),
NextState("FPU_IDLE")
).Elif((self.fmadd | self.fmsub | self.fnmadd | self.fnmsub) & ((self.e2 == 0) & (self.m2 == 0)), # Nothing to add (w/o sign!)
If(self.fnmadd | self.fnmsub, # sign3/e3/m3 used in FRESULT
NextValue(self.sign3, ~self.sign3) # Invert result finally
),
NextState("FRESULT") # Just supply (normalized finally!) result from multiplication!
).Else( # Ok, valid floats supplied ...
NextValue(self.s_bit, 0),
@ -267,6 +270,9 @@ class Risq5FPUDecoder(Module):
NextValue(self.m3, self.m3 + self.s_bit),
NextState("FADD8") # Adjust possible overflow ...
).Else( # Nope, all ready
If(self.fnmadd | self.fnmsub, # sign3/e3/m3 used in FRESULT
NextValue(self.sign3, ~self.sign3) # Invert result finally
),
NextState("FRESULT")
)
)
@ -277,6 +283,9 @@ class Risq5FPUDecoder(Module):
NextValue(self.m3, self.m3 >> 1), # Adjust mantissa & increment exponent
NextValue(self.e3, self.e3 + 1)
),
If(self.fnmadd | self.fnmsub, # sign3/e3/m3 used in FRESULT
NextValue(self.sign3, ~self.sign3) # Invert result finally
),
NextState("FRESULT")
) # End of fadd.s processing
@ -379,8 +388,7 @@ class Risq5FPUDecoder(Module):
# TODO: e3=se3 omitted ok?
If(self.fmul, # Simple multiplication
NextState("FRESULT")
).Else( # Fused multiply-add?
NextValue(self.sign3, self.sign3 ^ (self.fnmadd | self.fnmsub)), # Negate mult. result w/ f<n>xxx
).Else( # Fused multiply-add?
NextState("FMADD1")
)
) # End of fmul.s processing

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