rs1 bit width for csrs now ok!

master
kaqu 1 year ago
parent c12e8aa6d3
commit c698098604
  1. 18
      libmodules/instruction_decode.py
  2. 18
      software/source/flwstw.c

@ -283,11 +283,11 @@ class Risq5Decoder(Module):
)
).Elif(regs.f3 == 0x07, # csrrci rd, csr, imm_i4 (csr read & clear immediate)
If(regs.imm_i == risq5defs.CSR_frm_id, # FPU special: Rounding mode
NextValue(regs.csr[risq5defs.CSR_fcsr][5:8], regs.csr[risq5defs.CSR_fcsr][5:8] & ~regs.rs1[0:3]), # fcsr[5:8]='frm'!
NextValue(regs.csr[risq5defs.CSR_fcsr][5:8], regs.csr[risq5defs.CSR_fcsr][5:8] & ~regs.opcode[15:18]), # fcsr[5:8]='frm'!
).Elif(regs.imm_i == risq5defs.CSR_fflags_id, # FPU special: Exception flags
NextValue(regs.csr[risq5defs.CSR_fcsr][0:5], regs.csr[risq5defs.CSR_fcsr][0:5] & ~regs.rs1[0:5]), # fcsr[0:5]='fflags'!
NextValue(regs.csr[risq5defs.CSR_fcsr][0:5], regs.csr[risq5defs.CSR_fcsr][0:5] & ~regs.opcode[15:20]), # fcsr[0:5]='fflags'!
).Else( # Any other ...
NextValue(regs.csr[regs.csrindex], regs.csr[regs.csrindex] & ~regs.rs1), # csr (new value)
NextValue(regs.csr[regs.csrindex], regs.csr[regs.csrindex] & ~regs.opcode[15:20]), # csr (new value)
)
).Elif(regs.f3 == 0x02, # csrrs rd, <csr>, rs1 (csr read & set)
If(regs.imm_i == risq5defs.CSR_frm_id, # FPU special: Rounding mode
@ -299,11 +299,11 @@ class Risq5Decoder(Module):
)
).Elif(regs.f3 == 0x06, # csrrsi rd, csr, imm_i4 (csr read & set immediate)
If(regs.imm_i == risq5defs.CSR_frm_id, # FPU special: Rounding mode
NextValue(regs.csr[risq5defs.CSR_fcsr][5:8], regs.csr[risq5defs.CSR_fcsr][5:8] | regs.rs1[0:3]), # fcsr[5:8]='frm'!
NextValue(regs.csr[risq5defs.CSR_fcsr][5:8], regs.csr[risq5defs.CSR_fcsr][5:8] | regs.opcode[15:18]), # fcsr[5:8]='frm'!
).Elif(regs.imm_i == risq5defs.CSR_fflags_id, # FPU special: Exception flags
NextValue(regs.csr[risq5defs.CSR_fcsr][0:5], regs.csr[risq5defs.CSR_fcsr][0:5] | regs.rs1[0:5]), # fcsr[0:5]='fflags'!
NextValue(regs.csr[risq5defs.CSR_fcsr][0:5], regs.csr[risq5defs.CSR_fcsr][0:5] | regs.opcode[15:20]), # fcsr[0:5]='fflags'!
).Else( # Any other ...
NextValue(regs.csr[regs.csrindex], regs.csr[regs.csrindex] | regs.rs1), # csr (new value)
NextValue(regs.csr[regs.csrindex], regs.csr[regs.csrindex] | regs.opcode[15:20]), # csr (new value)
)
).Elif(regs.f3 == 0x01, # csrrw rd, csr, rs1 (csr read & write)
If(regs.imm_i == risq5defs.CSR_frm_id, # FPU special: Rounding mode
@ -315,11 +315,11 @@ class Risq5Decoder(Module):
)
).Elif(regs.f3 == 0x05, # csrrwi rd, csr, imm_i4 (csr read & write immediate)
If(regs.imm_i == risq5defs.CSR_frm_id, # FPU special: Rounding mode
NextValue(regs.csr[risq5defs.CSR_fcsr][5:8], regs.rs1[0:3]), # fcsr[5:8]='frm'!
NextValue(regs.csr[risq5defs.CSR_fcsr][5:8], regs.opcode[15:18]), # fcsr[5:8]='frm'!
).Elif(regs.imm_i == risq5defs.CSR_fflags_id, # FPU special: Exception flags
NextValue(regs.csr[risq5defs.CSR_fcsr][0:5], regs.rs1[0:5]), # fcsr[0:5]='fflags'!
NextValue(regs.csr[risq5defs.CSR_fcsr][0:5], regs.opcode[15:20]), # fcsr[0:5]='fflags'!
).Else( # Any other ...
NextValue(regs.csr[regs.csrindex], regs.rs1), # csr (new value)
NextValue(regs.csr[regs.csrindex], regs.opcode[15:20]), # csr (new value)
)
),
),

@ -5,6 +5,24 @@ static void start(void)
auipc ra,0 # Store current pc \n\
lui sp,%hi(0x40192000) # Setup stack pointer \n\
addi sp,sp,%lo(0x40192000) # s.a. \n\
mv x3,x0 # Clear \n\
fscsr x3 # Swap csr \n\
frcsr x3 # Control \n\
mv x3,x0 # Clear \n\
addi x3,x3,0x07 # rm=010 flags=10101 \n\
fscsr x3 # Swap csr \n\
frflags x3 # 001 x3=exception flags (OF etc., csrrs rd,fflags,x0) \n\
frcsr x3 # Control \n\
fsflagsi x0,0x08 # 001 x3=except.flags, (csrrwi rd,frm,rs1) \n\
frflags x3 # 001 x3=exception flags (OF etc., csrrs rd,fflags,x0) \n\
mv x3,x0 # Clear \n\
addi x3,x3,0x07 # rm=010 flags=10101 \n\
fsflags x3 \n\
frflags x3 # 001 x3=exception flags (OF etc., csrrs rd,fflags,x0) \n\
frcsr x3 # Control \n\
fsflagsi x0,0x0F # 001 x3=except.flags, (csrrwi rd,frm,rs1) \n\
frflags x3 # 001 x3=exception flags (OF etc., csrrs rd,fflags,x0) \n\
frcsr x3 # Control \n\
fsflagsi x0,0x18 # FEHLER!!! 001 x3=except.flags, (csrrwi rd,frm,rs1) \n\
frflags x3 # 001 x3=exception flags (OF etc., csrrs rd,fflags,x0) \n\
frcsr x3 # Control \n\

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