fsflagsi still defective ...

master
kaqu 2 years ago
parent 0e38f54ac0
commit c12e8aa6d3
  1. 24
      libmodules/risq5defs.py
  2. 6
      software/source/flwstw.c

@ -20,21 +20,21 @@ CSR_mepc = 6 # 0x341 mepc (Machine exception pc)
CSR_mscratch = 7 #0x340 mscratch (Machine scratch)
CSR_0xBC0 = 8 # 0xBC0 custom shadow register (read/write)
# Static parts (read only)
CSR_misa = 9 # 0x301 misa (Machine ISA)
CSR_mvendorid = 10 # 0xF11 mvendorid (Machine vendor ID)
CSR_marchid = 11 # 0xF12 marchid (Machine base microarchitecture)
CSR_mimpid = 12 # 0xF13 mimpid (Machine base microarchitecture version)
CSR_mhartid = 13 # 0xF14 mhartid (Machine hardware thread ('core') ID)
CSR_0xFC0 = 14 # 0xFC0 custom shadow register
# F-Extension
CSR_fflags = 15 # 0x001 fflags
CSR_frm = 16 # 0x002 frm
CSR_fcsr = 17 # 0x003 fcsr
CSR_fflags = 9 # 0x001 fflags
CSR_frm = 10 # 0x002 frm
CSR_fcsr = 11 # 0x003 fcsr
# Static parts (read only)
CSR_misa = 12 # 0x301 misa (Machine ISA)
CSR_mvendorid = 13 # 0xF11 mvendorid (Machine vendor ID)
CSR_marchid = 14 # 0xF12 marchid (Machine base microarchitecture)
CSR_mimpid = 15 # 0xF13 mimpid (Machine base microarchitecture version)
CSR_mhartid = 16 # 0xF14 mhartid (Machine hardware thread ('core') ID)
CSR_0xFC0 = 17 # 0xFC0 custom shadow register
# Sentinel
CSR_dummy = 15 # Shall never occurr ...
CSR_dummy = 18 # Shall never occurr ...
# RISC-V opcode defs.
CSR_mstatus_id = 0x300 # mstatus by default (Interrupt enable & stati)

@ -5,6 +5,9 @@ static void start(void)
auipc ra,0 # Store current pc \n\
lui sp,%hi(0x40192000) # Setup stack pointer \n\
addi sp,sp,%lo(0x40192000) # s.a. \n\
fsflagsi x0,0x18 # FEHLER!!! 001 x3=except.flags, (csrrwi rd,frm,rs1) \n\
frflags x3 # 001 x3=exception flags (OF etc., csrrs rd,fflags,x0) \n\
frcsr x3 # Control \n\
mv x3,x0 # Clear \n\
addi x3,x3,0x55 # rm=010 flags=10101 \n\
fscsr x0,x3 # Swap csr \n\
@ -14,8 +17,9 @@ static void start(void)
#fscsr x3,x0 # 003 x3=fcs,fcs=x0 (csrrw rd,fcsr,rs1) \n\
fsrmi x0,3 # 002 x3=round.mod., rm=3 (csrrwi rd,frm,rs1) \n\
frrm x3 # 002 x3=rounding mode (rtz etc., csrrs rd,frm,x0) \n\
fsflagsi x0,0x18 # 001 x3=except.flags, (csrrwi rd,frm,rs1) \n\
fsflagsi x0,0x18 # FEHLER!!! 001 x3=except.flags, (csrrwi rd,frm,rs1) \n\
frflags x3 # 001 x3=exception flags (OF etc., csrrs rd,fflags,x0) \n\
frcsr x3 # Control \n\
mv x3,x0 # Clear \n\
addi x3,x3,0x1F # flags=10101 \n\
fsflags x0,x3 # 001 x3=except.flags (csrrw rd,fflags,rs1) \n\

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