The core consists of an L1 cache for program code loading (or L0 is it 🤔 ?), a 'data' load unit (LU) & the
corresponding store unit (SU), the base & FPU decoders as well as the data flow control logic (disturbingly called ALU - 🗣 respect the historical context!). The data flow is controllable via the Wishbone system bus
(even remotely!). All units are implemented w/ migen's finite state machines (FSMs).
The L1 cache loads itself upon boot (RISC-V: from address 0) and signals 'ready' to the data flow unit, which in turn loads the 1st opcode (by pure coincidence the program counter (PC) starts from this location
as well 🎉 !).
If run is enabled in the cpu mode control word, the decoder processes (executes) the opcode.
The opcode dictates the PC modification when finishing (+4 bytes = next opcode, others by jumps/branches or interrupts). L1 cache (re-)loads are triggered as necessary ...
Graphic shows the base ('I') decoder together w/ the 'M' extension (integer multiply/divide). The FPU
decoder is triggered via the base decoder (not shown here) which then simply waits for termination of the individual processing chains.
#### 3.2 Program structure: ####
1. risq5.py - this is the main FPGA building source
2. libmodules subdir - all RISC-V sources, DRAM DMA loader helper & system time support
3. helpers subdir - contains python helpers for load & flash etc.