More readme files ...

README.md

@@ -37,7 +37,25 @@ https://saturn.ffzg.hr/rot13/index.cgi?colorlight_5a_75b
 https://github.com/trabucayre/litexOnColorlightLab004/  
 https://blog.pcbxprt.com/index.php/2020/07/19/running-risc-v-core-on-small-fpga-board/
 
-## Program structure: ##
+
+### 3. Functional description ☯ ...💡!
+
+#### 3.1 General ####
+
+The core consists of an L1 cache for program code loading (or L0 is it 🤔 ?), a 'data' load unit (LU) & the
+corresponding store unit (SU), the base & FPU decoders as well as the data flow control logic (disturbingly called ALU - 🗣 respect the historical context!). The data flow is controllable via the Wishbone system bus 
+(even remotely!). All units are implemented w/ migen's finite state machines (FSMs).  
+The L1 cache loads itself upon boot (RISC-V: from address 0) and signals 'ready' to the data flow unit, which in turn loads the 1st opcode (by pure coincidence the program counter (PC) starts from this location 
+as well 🎉 !). 
+If run is enabled in the cpu mode control word, the decoder processes (executes) the opcode.  
+The opcode dictates the PC modification when finishing (+4 bytes = next opcode, others by jumps/branches or interrupts). L1 cache (re-)loads are triggered as necessary ...  
+
+![Main Decoder](./impress/InstructionDecoder.png)
+
+Graphic shows the base ('I') decoder together w/ the 'M' extension (integer multiply/divide). The FPU
+decoder is triggered via the base decoder (not shown here) which then simply waits for termination of the individual processing chains.
+
+#### 3.2 Program structure: ####
 1. risq5.py - this is the main FPGA building source
 2. libmodules subdir - all RISC-V sources, DRAM DMA loader helper & system time support
 3. helpers subdir - contains python helpers for load & flash etc.
@@ -46,9 +64,9 @@ https://blog.pcbxprt.com/index.php/2020/07/19/running-risc-v-core-on-small-fpga-
 6. software subdir - contains a separate build, load & flash logic for RV32IMF application code
 7. litex subdir - contains modified LiteX sources (& originals)
 8. impress subdir - impress graphics to improve understanding
-(the rest currently is of minor importance ...)
+(the rest is of minor importance currently ...)
 
-## Quickstart ##
+#### 3.3 Quickstart ####
 
 After installation of the relevant toolchains:
 1. Open the project in VSC (or use your favourite IDE & maybe adjust some settings ;), adjust local paths if nec. ...
@@ -57,14 +75,14 @@ After installation of the relevant toolchains:
    --build --load --revision=7.0 --uart-name=crossover --with-etherbone --ip-address=192.168.1.20 --csr-csv=build/csr.csv --isa-extension-m --isa-extension-f --doc
    to create & load the project to on-board SRAM via the USB/JTAG-Adapter (this takes it's time ...)
 
-## Test assembly code ##
+#### 3.4 Test assembly code ####
 1. This time, open up a terminal & cd to the project local 'software' subdirectory
 2. You can load an application to absolute location 0x40190000 (you may have to adjust local paths!):  
 	./testloader.sh flwstw
 3. Run the debugger: risq5dbg.py with the same options as above (for risq5.py)
 4. You're now able to verify correct operations of the cpu (well, hopefully 😎!)
 
-## Some - maybe helpful - references for implementing IEEE 754 FPU logic: ##
+### Some - maybe helpful - references for implementing IEEE 754 FPU logic: ###
 - [IEEE 754 simulator](https://www.h-schmidt.net/FloatConverter/IEEE754.html)  
 - [IEEE 754 format usage](https://www.pitt.edu/~juy9/142/slides/L3-FP_Representation.pdf)  
 - [same as above](https://cs.boisestate.edu/~alark/cs354/lectures/ieee754.pdf)  

firmware/README.md

@@ -1,5 +1,7 @@
 # FIRMWARE #
 
+*** Currently of no importance for this project ***
+
 This directory contains the modified versions of several BIOS related files.
 The modifications are:
 

helpers/README.md

@@ -7,4 +7,4 @@ This directory contains helper & test routines.
 3. load_to_flash.py - Used by main build to flash the FPGA data (includes 'ROM' software BIOS)  
     also may be called directly, then (currently) uses eraser.svf to clear all flash data (reset!)  
 4. prepare_firmware.py - Used by main build to integrate modified BIOS routines into main LiteX build
-5. remotetest.py - Test drive the LED driver remotely via wishbone bus (i.e. network)
+5. remotetest.py - DRAM read/write test

impress/README.md

@@ -0,0 +1,7 @@
+# IMPRESS #
+
+This directory contains explanatory drawings for LibreOffice/Impress:
+
+1. Situation_guide.odp - Shows Wishbone system bus access, memory access & DRAM loading on several slides
+2. InstructionDecode.odp - The base instruction decoder automaton
+3. Address_space.odp - Colorlight board arrangement, in this context currently of no importance ...