4 regs reduced variant started, debugger adjust

master
kaqu 2 years ago
parent 24c02c7835
commit 9cdfa9edba
  1. 10
      debugger/dbgeval.py
  2. 143
      debugger/qt5dbg.py
  3. 1
      debugger/risq5dbg.py
  4. 8
      libmodules/core.py
  5. 34
      libmodules/register_file.py
  6. 4
      risq5_fpu.py
  7. 20
      software/source/flwstw.c
  8. 2
      software/testloader.sh

@ -11,6 +11,12 @@ x_description = [ # Pseudo reg. naming ...
" a6", " a7", " s2", " s3", " s4", " s5", " s6", " s7",
" s8", " s9", " s10", " s11", " t3", " t4", " t5", " t6"
]
f_description = [ # Pseudo reg. naming ...
" ft0", " ft1", " ft2", " ft3", " ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1", " fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3", " fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11", " ft8", " ft9", "ft10", "ft11"
]
csr_description = {
0x300 : "mstatus",
@ -215,6 +221,10 @@ def disassemble(opcode, pc):
msg = "fence.i (ignored)"
else:
msg = "fence {0} (ignored)".format(hex(opcode))
elif op == 0x07:
msg = "flw {0},{1}({2})".format(f_description[rd], hex(imm_i), x_description[rs1])
elif op == 0x27:
msg = "fsw {0},{1}({2})".format(f_description[rs2], hex(imm_s), x_description[rs1])
else:
msg = "-- illegal? --"
print("Illegal opcode detected: {0} @{1}?".format(hex(opcode),hex(pc)))

@ -16,7 +16,7 @@ from PyQt5.QtWidgets import *
from PyQt5.QtCore import Qt, QTimer, pyqtSlot
from PyQt5.QtGui import QPainter, QBrush, QPen, QFont, QFontMetrics, QColor
from dbgeval import x_description, flag, disassemble
from dbgeval import x_description, f_description, flag, disassemble
class dbgWindow(QMainWindow):
"""Qt5 base class"""
@ -37,9 +37,11 @@ class dbgWindow(QMainWindow):
self.widget = QWidget() # Central layout widget
# Prepare x<n> regs displays
self.MAXLABEL = 32
self.MAXLABEL = 4 # 32 regs/fregs originally! But won't fit on ColorLight ...
self.lblList = list() # All input/output fields
self.txtList = list()
self.lblFList = list() # F-Extension float registers
self.txtFList = list()
for i in range(self.MAXLABEL):
q = QLabel("{0}(x{1})".format(x_description[i], i)) # For now, may become entry field later ...
q.setFixedWidth(80)
@ -50,6 +52,16 @@ class dbgWindow(QMainWindow):
q2.textEdited.connect(lambda msg=str(i),i=i: self.on_textEdited(msg,i))
self.txtList.append(q2)
for i in range(self.MAXLABEL):
q = QLabel("{0}(f{1})".format(f_description[i], i)) # For now, may become entry field later ...
q.setFixedWidth(80)
self.lblFList.append(q)
q2 = QLineEdit("0x00000000")
q2.setFixedWidth(160)
q2.returnPressed.connect(lambda i=i: self.on_returnFPressed(i)) # Nice trick! (Or awkward solution rather)
q2.textEdited.connect(lambda msg=str(i),i=i: self.on_textEdited(msg,i))
self.txtFList.append(q2)
self.vbox1 = QVBoxLayout()
self.vbox1.setAlignment(Qt.AlignTop) # Won't move w/ resize!
@ -70,6 +82,7 @@ class dbgWindow(QMainWindow):
for i in range(0, 4):
self.hbox1.addWidget(self.lblList[i])
self.hbox1.addWidget(self.txtList[i])
# zero/x1
self.txtList[0].setStyleSheet("background-color: gray; border: 1px solid black;")
self.txtList[0].setEnabled(False) # Not changeable
@ -78,45 +91,52 @@ class dbgWindow(QMainWindow):
# sp/x2
self.txtList[2].setStyleSheet("background-color: lightblue; border: 1px solid black;")
self.hbox2 = QHBoxLayout() # Row of regs (x4 .. x7)
self.hbox2.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(4, 8):
self.hbox2.addWidget(self.lblList[i])
self.hbox2.addWidget(self.txtList[i])
self.hbox3 = QHBoxLayout() # Row of regs (x8 .. x11)
self.hbox3.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(8, 12):
self.hbox3.addWidget(self.lblList[i])
self.hbox3.addWidget(self.txtList[i])
# fp/x8
self.txtList[8].setStyleSheet("background-color: lightyellow; border: 1px solid black;")
if self.MAXLABEL > 4: # Only for non-reduced version (32 regs/fregs)
self.hbox2 = QHBoxLayout() # Row of regs (x4 .. x7)
self.hbox2.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(4, 8):
self.hbox2.addWidget(self.lblList[i])
self.hbox2.addWidget(self.txtList[i])
self.hbox3 = QHBoxLayout() # Row of regs (x8 .. x11)
self.hbox3.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(8, 12):
self.hbox3.addWidget(self.lblList[i])
self.hbox3.addWidget(self.txtList[i])
# fp/x8
self.txtList[8].setStyleSheet("background-color: lightyellow; border: 1px solid black;")
self.hbox4 = QHBoxLayout() # Row of regs (x12 .. x15)
self.hbox4.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(12, 16):
self.hbox4.addWidget(self.lblList[i])
self.hbox4.addWidget(self.txtList[i])
self.hbox5 = QHBoxLayout() # Row of regs (x16 .. x19)
self.hbox5.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(16, 20):
self.hbox5.addWidget(self.lblList[i])
self.hbox5.addWidget(self.txtList[i])
self.hbox6 = QHBoxLayout() # Row of regs (x20 .. x23)
self.hbox6.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(20, 24):
self.hbox6.addWidget(self.lblList[i])
self.hbox6.addWidget(self.txtList[i])
self.hbox7 = QHBoxLayout() # Row of regs (x24 .. x27)
self.hbox7.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(24, 28):
self.hbox7.addWidget(self.lblList[i])
self.hbox7.addWidget(self.txtList[i])
self.hbox8 = QHBoxLayout() # Row of regs (x28 .. x31)
self.hbox8.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(28, 32):
self.hbox8.addWidget(self.lblList[i])
self.hbox8.addWidget(self.txtList[i])
else:
self.hbox2 = QHBoxLayout() # Row of regs (x4 .. x7)
self.hbox2.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(0, 4):
self.hbox2.addWidget(self.lblFList[i])
self.hbox2.addWidget(self.txtFList[i])
self.hbox4 = QHBoxLayout() # Row of regs (x12 .. x15)
self.hbox4.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(12, 16):
self.hbox4.addWidget(self.lblList[i])
self.hbox4.addWidget(self.txtList[i])
self.hbox5 = QHBoxLayout() # Row of regs (x16 .. x19)
self.hbox5.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(16, 20):
self.hbox5.addWidget(self.lblList[i])
self.hbox5.addWidget(self.txtList[i])
self.hbox6 = QHBoxLayout() # Row of regs (x20 .. x23)
self.hbox6.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(20, 24):
self.hbox6.addWidget(self.lblList[i])
self.hbox6.addWidget(self.txtList[i])
self.hbox7 = QHBoxLayout() # Row of regs (x24 .. x27)
self.hbox7.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(24, 28):
self.hbox7.addWidget(self.lblList[i])
self.hbox7.addWidget(self.txtList[i])
self.hbox8 = QHBoxLayout() # Row of regs (x28 .. x31)
self.hbox8.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
for i in range(28, 32):
self.hbox8.addWidget(self.lblList[i])
self.hbox8.addWidget(self.txtList[i])
self.hbox9 = QHBoxLayout() # Buttons, row #1
self.hbox9.setAlignment(Qt.AlignLeft) # Won't move w/ resize!
self.qpbPC = QLabel("PC")
@ -192,13 +212,14 @@ class dbgWindow(QMainWindow):
self.vbox1.addLayout(self.hbox0, 1)
self.vbox1.addLayout(self.hbox1, 1)
self.vbox1.addLayout(self.hbox2, 1)
self.vbox1.addLayout(self.hbox3, 1)
self.vbox1.addLayout(self.hbox4, 1)
self.vbox1.addLayout(self.hbox5, 1)
self.vbox1.addLayout(self.hbox6, 1)
self.vbox1.addLayout(self.hbox7, 1)
self.vbox1.addLayout(self.hbox8, 1)
self.vbox1.addLayout(self.hbox2, 1) # Recycled for float regs!
if self.MAXLABEL > 4: # Only w/ full register list (32 regs/fregs)
self.vbox1.addLayout(self.hbox3, 1)
self.vbox1.addLayout(self.hbox4, 1)
self.vbox1.addLayout(self.hbox5, 1)
self.vbox1.addLayout(self.hbox6, 1)
self.vbox1.addLayout(self.hbox7, 1)
self.vbox1.addLayout(self.hbox8, 1)
self.vbox1.addLayout(self.hbox10, 2)
self.vbox1.addLayout(self.hbox11, 2)
self.vbox1.addLayout(self.hbox12, 2)
@ -291,10 +312,18 @@ class dbgWindow(QMainWindow):
i32NextPC = self.wb.regs.risq5ext_b32_next_pc.read()
self.txtNextPC.setText("0x{:08X}".format(i32NextPC))
for i in range(32): # Walk x<n> register file
for i in range(self.MAXLABEL): # Walk x<n> register file
self.wb.regs.risq5ext_b5_wb_reg_no.write(i) # Select register
val = self.wb.regs.risq5ext_b32_wb_reg_value_r.read() # Pick actual register risq5_b32_wb_reg_value_r
self.txtList[i].setText("0x{:08X}".format(val))
# F-Extension float registers
for i in range(self.MAXLABEL): # Walk f<n> register file
self.wb.regs.risq5ext_b5_wb_reg_no.write(i) # Select register
val = self.wb.regs.risq5ext_b32_wb_freg_value_r.read() # Pick actual register risq5_b32_wb_reg_value_r
val = val # Translate hex value -> decimal float!
self.txtFList[i].setText("0x{:08X}".format(val))
pc = self.wb.regs.risq5ext_b32_PC.read()
self.txtPC.setText("0x{:08X}".format(pc))
opcode = self.wb.regs.risq5ext_b32_opcode.read()
@ -338,6 +367,24 @@ class dbgWindow(QMainWindow):
self.qpbUpdate.setVisible(False)
self.timer.start() # Re-enable timer event
@pyqtSlot()
def on_returnFPressed(self, index):
self.timer.stop() # Block interference
sender = self.sender() # Where are we coming from?
try:
# TODO: Translate decimal to hex value 1st!
b32Value = int(sender.text(),16) # Get hex value
#print("x{0} new value: {1}".format(index, b32Value))
self.wb.regs.risq5ext_b5_wb_reg_no.write(index) # Write index
self.wb.regs.risq5ext_b32_wb_reg_value_w.write(b32Value) # New value
self.wb.regs.risq5ext_b1_wb_freg_we.write(1) # Write float request (pulse)
time.sleep(0.05) # Just make sure ...
except:
pass
self.wb.regs.risq5ext_b1_wb_freg_we.write(0) # Write request (pulse)
self.qpbUpdate.setVisible(False)
self.timer.start() # Re-enable timer event
@pyqtSlot()
def on_clickNextStep(self):
self.timer.stop()

@ -58,6 +58,7 @@ def main():
parser.add_argument("--flash", action="store_true", help="not used")
parser.add_argument("--uart-name", default="crossover", help="not used")
parser.add_argument("--isa-extension-m", action="store_true", help="RISC-V extension M")
parser.add_argument("--isa-extension-f", action="store_true", help="RISC-V extension F")
parser.add_argument("--with-bios-for-none", action="store_true", help="Create ROM w/ BIOS even w/o CPU")
args = parser.parse_args()

@ -59,7 +59,7 @@ class Risq5Core(Module, AutoCSR, AutoDoc, ModuleDoc):
:b32_FSMs: FSM states
"""
def __init__(self, RAMWaitTime=128, LU_CacheWait=24, L1CacheSize=8, L1Cache=None, LUCacheSize=4, LUCache=None, SU_Unit=None, clint=None, isa_extensions=0x40000100):
def __init__(self, RAMWaitTime=128, LU_CacheWait=24, L1CacheSize=8, L1Cache=None, LUCacheSize=4, LUCache=None, SU_Unit=None, clint=None, isa_extensions=0x40000100, CPUREGS=32, CPUREGADDRESSBITS=5):
# Inputs
self.b32mode = CSRStorage(32, reset_less=True,
@ -112,8 +112,8 @@ class Risq5Core(Module, AutoCSR, AutoDoc, ModuleDoc):
description="""
New PC address (if ``b32mode[4]`` is set)
""")
self.b5_wb_reg_no = CSRStorage(5, reset_less=True,
fields=[CSRField("wb_reg_no", size=5, description="*Field*: 5-Bit value")],
self.b5_wb_reg_no = CSRStorage(CPUREGADDRESSBITS, reset_less=True,
fields=[CSRField("wb_reg_no", size=CPUREGADDRESSBITS, description="*Field*: 5-Bit value")],
description="""
Register index to read or write remotely
""")
@ -183,7 +183,7 @@ class Risq5Core(Module, AutoCSR, AutoDoc, ModuleDoc):
# Local vars.
# Register file ----------------------------------------------------------------------------
self.submodules.regs = regs = Risq5RegisterFile()
self.submodules.regs = regs = Risq5RegisterFile(CPUREGS, CPUREGADDRESSBITS)
self.sync += [ # External register file write port (debugger)
regs.write_ext_index.eq(self.b5_wb_reg_no.storage), # Let write index follow
regs.ext_wrport.dat_w.eq(self.b32_wb_reg_value_w.storage), # & value as well ...

@ -22,7 +22,7 @@ class Risq5RegisterFile(Module):
"""
Risq5 The RISC-V register file
"""
def __init__(self):
def __init__(self, CPUREGS=32, CPUREGADDRESSBITS=5):
# Register file ----------------------------------------------------------------------------
WORDSIZE = 32
@ -30,12 +30,12 @@ class Risq5RegisterFile(Module):
self.opcode = Signal(WORDSIZE, reset_less=True) # Loaded from instruction fetch
# Instruction decode, 32 bit opcode parts --------------------------------------------------
self.op = Signal(7, reset_less=True) # [6:0] Instruction type
self.rd = Signal(5, reset_less=True) # [11:7] Destination register
self.f3 = Signal(3, reset_less=True) # [14:12] Instruction type modifier
self.rs1 = Signal(5, reset_less=True) # [19:15] source register #1
self.rs2 = Signal(5, reset_less=True) # [24:20] source register #2
self.f7 = Signal(7, reset_less=True) # [31:25] Instruction type modifier
self.op = Signal(7, reset_less=True) # [6:0] Instruction type
self.rd = Signal(CPUREGADDRESSBITS, reset_less=True) # [11:7] Destination register
self.f3 = Signal(3, reset_less=True) # [14:12] Instruction type modifier
self.rs1 = Signal(CPUREGADDRESSBITS, reset_less=True) # [19:15] source register #1
self.rs2 = Signal(CPUREGADDRESSBITS, reset_less=True) # [24:20] source register #2
self.f7 = Signal(7, reset_less=True) # [31:25] Instruction type modifier
self.imm_i = Signal((12, True), reset_less=True) # Immediates (usually: signed) & CSR(!)
self.imm_s = Signal((12, True), reset_less=True)
self.imm_b = Signal((13, True), reset_less=True)
@ -67,8 +67,8 @@ class Risq5RegisterFile(Module):
self.imm_j.eq(Cat(0,self.opcode[21:31], self.opcode[20], self.opcode[12:20], self.opcode[31])),
]
self.read_ext_index = Signal(5, reset_less=True) # External read access (index)
self.write_ext_index = Signal(5, reset_less=True) # External write access (index)
self.read_ext_index = Signal(CPUREGADDRESSBITS, reset_less=True) # External read access (index)
self.write_ext_index = Signal(CPUREGADDRESSBITS, reset_less=True) # External write access (index)
self.xs1u = Signal(32, reset_less=True) # Value of source register #1 (unsigned)
self.xs2u = Signal(32, reset_less=True) # Value of source register #2 (unsigned)
self.xs1s = Signal((32,True), reset_less=True) # Signed register #1
@ -84,7 +84,7 @@ class Risq5RegisterFile(Module):
self.LUAddress = Signal(32, reset_less=True) # Load unit address to use
self.SUAddress = Signal(32, reset_less=True) # Store unit address to use
regs = Memory(WORDSIZE, 32) # 32-bit, 32 elements -> x0 .. x31
regs = Memory(WORDSIZE, CPUREGS) #32) # 32-bit, 32 elements -> x0 .. x31
self.specials += regs
# rd -> index register to write
self.rd_wrport = regs.get_port(write_capable=True) # Internal register file access
@ -125,15 +125,15 @@ class Risq5RegisterFile(Module):
# -------------------------- F extension ---------------------------------------------------
# Risq5 floating point unit (FPU extension)
# Instruction decode, 32 bit opcode parts --------------------------------------------------
self.frd = Signal(5, reset_less=True) # [11:7] Destination register
self.frd = Signal(CPUREGADDRESSBITS, reset_less=True) # [11:7] Destination register
#self.rm = Signal(3, reset_less=True) # [14:12] Instruction type modifier
self.frs1 = Signal(5, reset_less=True) # [19:15] source register #1
self.frs2 = Signal(5, reset_less=True) # [24:20] source register #2
self.frs3 = Signal(5, reset_less=True) # [31:27] Instruction type modifier
self.fread_ext_index = Signal(5, reset_less=True) # External read access (index)
self.fwrite_ext_index = Signal(5, reset_less=True) # External write access (index)
self.frs1 = Signal(CPUREGADDRESSBITS, reset_less=True) # [19:15] source register #1
self.frs2 = Signal(CPUREGADDRESSBITS, reset_less=True) # [24:20] source register #2
self.frs3 = Signal(CPUREGADDRESSBITS, reset_less=True) # [31:27] Instruction type modifier
self.fread_ext_index = Signal(CPUREGADDRESSBITS, reset_less=True) # External read access (index)
self.fwrite_ext_index = Signal(CPUREGADDRESSBITS, reset_less=True) # External write access (index)
fregs = Memory(WORDSIZE, 32) # 32-bit, 32 elements -> f0 .. f31
fregs = Memory(WORDSIZE, CPUREGS) #32) # 32-bit, 32 elements -> f0 .. f31
self.specials += fregs
# rd -> index register to write
self.frd_wrport = fregs.get_port(write_capable=True) # Internal register file access

@ -260,7 +260,9 @@ class BaseSoC(SoCCore):
LUCache=dramtransfer2,
SU_Unit=fpga2dram,
clint=clint,
isa_extensions=isa_extensions # Custom value from global var
isa_extensions=isa_extensions, # Custom value from global var
CPUREGS=4, # 32 regularly, won't fit w/ F-Extension on Colorlight
CPUREGADDRESSBITS=2 # 5 regularly, won't fit w/ F-Extension on Colorlight
)
self.add_csr("risq5ext")

@ -0,0 +1,20 @@
#pragma GCC diagnostic ignored "-Wunused-function"
static void start(void)
{
__asm__ __volatile__ ("\
auipc ra,0 # Store current pc \n\
lui sp,%hi(0x40192000) # Setup stack pointer \n\
addi sp,sp,%lo(0x40192000) # s.a. \n\
li x3, 123 # Load \n\
sw x3,0(sp) # Save to stack \n\
flw f0,0(sp) # Load float from stack \n\
nop # ... \n\
");
#include "onek_nops.c"
#include "onek_nops.c"
#include "onek_nops.c"
#include "onek_nops.c"
}

@ -27,7 +27,7 @@ export PATH=$PATH:$MY_LOCAL_LITEX_PATH/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x
TRIPLE="riscv64-unknown-elf"
CPU="vexriscv"
CPUFLAGS="-march=rv32im -mabi=ilp32 -D__vexriscv__"
CPUFLAGS="-march=rv32imf -mabi=ilp32 -D__vexriscv__"
CPUENDIANNESS="little"
CPU_DIRECTORY="$MY_LOCAL_LITEX_PATH/litex/litex/soc/cores/cpu/vexriscv"
COMPILER_RT_DIRECTORY="$MY_LOCAL_LITEX_PATH/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data"

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