Fused add preparation incomplete (fixed)

master
kaqu 1 year ago
parent 65f8b68817
commit 9b0f34a1c2
  1. 3
      libmodules/fpu_decode.py

@ -385,12 +385,15 @@ class Risq5FPUDecoder(Module):
)
) # End of fmul.s processing
FPU_fsm.act("FMADD1",
# Result: sign3/e3/m3 -> new fs1: sign1/e1/m1, fs3 -> new fs2: sign2/e2/m2
NextValue(self.sign1, self.sign3), # Negate mult. result w/ f<n>xxx
NextValue(self.sign2, regs.fs3[31] ^ (self.fmsub | self.fnmsub)), # Invert sign for subtraction!
NextValue(self.e1, self.e3),
NextValue(self.e2, regs.fs3[23:31] - 127),
NextValue(self.m1, Cat(0,0,0, self.m3[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
NextValue(self.m2, Cat(0,0,0, regs.fs3[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
NextValue(self.fs1, Cat(self.m3[0:23], (self.e3+127)[0:8], self.sign3)),
NextValue(self.fs2, self.fs3),
NextState("FADD1")
)

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