ROM avail. w/ bus not accessible?! Interrupts miss

master
kaqu 2 years ago
parent 0654612b46
commit 9676712e54
  1. 6
      litex/litex/soc/integration/soc_core.py
  2. 31
      risq5_wo_vex.py

@ -132,8 +132,10 @@ class SoCCore(LiteXSoC):
self.cpu_variant = cpu_variant
self.cpu_cls = cpu_cls
if cpu_type in [None, "zynq7000"]:
integrated_rom_size = 0
# 25.02.21/KQ Removed: if cpu_type in [None, "zynq7000"]:
# TODO: w/o bios -> reverse! Saves 10 minutes translation time!
if cpu_type in ["zynq7000"]:
integrated_rom_size = 0 # Otherwise: remains 32Kb
self.integrated_rom_size = integrated_rom_size
self.integrated_rom_initialized = integrated_rom_init != []
self.integrated_sram_size = integrated_sram_size

@ -53,11 +53,11 @@ from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage, CSRField
from litex.soc.interconnect.stream import SyncFIFO # <-- !
from litex.soc.interconnect.stream import SyncFIFO
from litedram.modules import M12L16161A, M12L64322A
from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
from litedram.frontend.dma import LiteDRAMDMAReader, LiteDRAMDMAWriter # <-- !
from litedram.frontend.dma import LiteDRAMDMAReader, LiteDRAMDMAWriter
from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
@ -139,7 +139,7 @@ class BaseSoC(SoCCore):
with_rst = kwargs["uart_name"] not in ["serial", "bridge"] # serial_rx shared with user_btn_n.
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform, sys_clk_freq, use_internal_osc=use_internal_osc, with_usb_pll=with_usb_pll,with_rst=with_rst, sdram_rate=sdram_rate)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
@ -159,11 +159,7 @@ class BaseSoC(SoCCore):
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# 24.02.21/KQ Intergrating ROM separately
from litex.soc.integration.soc import SoCRegion
self.bus.add_region("rom", SoCRegion(origin=0, size=0x00008000))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
@ -178,9 +174,10 @@ class BaseSoC(SoCCore):
ip_address = ip_address,
mac_address = mac_address,
)
# FIXME: Added 2nd master to csr (after master0)
from litex.soc.interconnect import wishbone
self.csr.add_master(name="cpu2csr", master=wishbone.Interface(8,14))
""" FIXME: Added 2nd master to csr (after master0)
##from litex.soc.interconnect import wishbone
##self.csr.add_master(name="cpu2csr", master=wishbone.Interface(8,14))
#from litex.soc.interconnect import wishbone
#self.cpu2csr = cpu2csr = wishbone.Interface()
# Signals: ack, adr(14), bte(2), cti(3), cyc, dat_r(8), dat_w(8), err, sel, stb, we
@ -189,16 +186,8 @@ class BaseSoC(SoCCore):
# Signals: adr(14), dat_r(8), dat_w(8), we
# data_width8, adr_width=14
#self.add_wb_master(self.etherbone.bus) # add_csr_bridge(self.mem_map["csr"], False) # fails
# Base counter (used for clocking)
#counter = Signal(32, reset_less=True) # 32-Bit counter
#self.sync += counter.eq(counter + 1)
# USERLED blink (on-board LED)
# only w/ uart-name=crossover option:
#if kwargs["uart_name"] not in ["serial", "bridge"]:
# self.comb += platform.request("user_led_n").eq(~(counter[23])) # ~2Hz
"""
# System time (count)
self.submodules.systime = systime = SysTime(comparecount=0x0000EA90)
self.add_csr("systime")

Loading…
Cancel
Save