Register need returns (cached?) old values ...

master
kaqu 2 years ago
parent 28e696bff3
commit 956d07c49d
  1. 2
      debugger/dbgeval.py
  2. 2
      debugger/risq5dbg.py
  3. 4
      libmodules/instruction_decode.py
  4. 8
      libmodules/systime.py
  5. 1
      software/source/testhardinterrupts.c
  6. 12
      software/source/testtimerinterrupt.c

@ -116,6 +116,8 @@ def disassemble(opcode, pc):
elif op == 0x6F: # J-Type (jal)
msg = "jal {0},{1}".format(x_description[rd], hex((pc+imm_j) & 0xFFFFFFFF))
elif op == 0x67: # I-Type (jalr)
if opcode == 0x00008067: # Special case: ret
msg = "ret ( jalr {0},{1}({2}) )".format(x_description[rd], hex(imm_i & 0xFFFFFFFF), x_description[rs1])
if f3 == 0x00:
msg = "jalr {0},{1}({2})".format(x_description[rd], hex(imm_i & 0xFFFFFFFF), x_description[rs1])
elif op == 0x73:

@ -28,7 +28,7 @@ def risq5dbg(csr_csv):
wb.regs.risq5_b32mode.write(1) # Enable run (but will halt before 1. instruction!)
print("PC adjusted to 0x40190000")
wb.regs.risq5_b32_next_pc.write(0x40190000) # Provide a new PC address
wb.regs.risq5_b32_next_pc.write(0x40190550) # Provide a new PC address
mode = wb.regs.risq5_b32mode.read() # Pick up current mode setting
wb.regs.risq5_b32mode.write(mode | 16) # Adjust PC, will load L1 2nd time now
wb.regs.risq5_b1_wb_reg_we.write(0) # Reset write requests (if any pending)

@ -209,8 +209,8 @@ class Risq5Decoder(Module):
),
NextValue(self.write, 1), # Trigger write rd
# fence & fence.i memory & i/o read/write ordering observation not implemented/ignored ...
#).Elif(regs.op == 0x0F, # I-Type (3) fence/fence.i
# NextValue(self.DECODE_state, 0x0F),
).Elif(regs.op == 0x0F, # I-Type (3) fence/fence.i
NextValue(self.DECODE_state, 0x0F), # No action at all!
).Elif((regs.op == 0x73) & (regs.f3 != 0x00), # I-Type (4) CSR access
# CSRs: mstatus,mip,mie,mcause,mtvec,mtval,mepc,mscratch (Machine mode [level 3] registers)
# misa,mvendorid,marchid,mimpid,mhartid (Identification registers)

@ -114,11 +114,13 @@ class Clint(Module, AutoCSR, AutoDoc, ModuleDoc):
##self.b32Counter.eq(self.b32Counter + 1), # Run system frequency counter
##If(self.b32Counter == comparecount, # Approx. 1ms
## self.b32Counter.eq(0),
If(self.mtimecmp.storage > 0, # Only, if timer comparison value set!
self.mtime.storage.eq(self.mtime.storage + 1), # Increment counter
If(self.mtimecmp.storage > 0, # Only, if timer comparison value set!
If(self.mtime.storage >= self.mtimecmp.storage, # Limit reached?
self.time_int_p.eq(1), # Set int
self.mtimecmp.storage.eq(0) # Clear timer comparison value
self.mtimecmp.storage.eq(0), # Clear timer comparison value
self.mtime.storage.eq(0) # Clear timer comparison value
).Else(
self.mtime.storage.eq(self.mtime.storage + 1), # Increment counter
)
).Else( # Not set (no more ...)
self.time_int_p.eq(0) # Reset int (pulse now)

@ -3,7 +3,6 @@ static void start(void)
{
__asm__ __volatile__ ("\
auipc ra,0 # Store current pc \n\
.word 0xFFFFFFFF # Invalid opcode \n\
lui t0,%hi(myint) # Make interrupt vector known \n\
addi t0,t0,%lo(myint) # \n\
csrw mtvec,t0 # Store actual address \n\

@ -1,8 +1,19 @@
#include "../../build/colorlight_5a_75b/software/include/generated/csr.h"
#pragma GCC diagnostic ignored "-Wunused-function"
static void setDownCounter(void)
{
clint_mtimecmp_write(clint_mtime_read()+0x100000); // Start timer
}
#pragma GCC diagnostic ignored "-Wunused-function"
static void start(void)
{
__asm__ __volatile__ ("\
auipc ra,0 # Store current pc \n\
lui sp,%hi(0x40192000) # Setup stack pointer \n\
addi sp,sp,%lo(0x40192000) # s.a. \n\
nop # ... \n\
lui t0,%hi(myint) # Make interrupt vector known \n\
addi t0,t0,%lo(myint) # \n\
csrw mtvec,t0 # Store actual address \n\
@ -24,6 +35,7 @@ loop: addi t0,t0,1 # Stupid job loop \n\
nop # \n\
myint: addi t1,t1,1 # Interrupt routine \n\
csrr t2,mcause # Figure out interrupt type \n\
call setDownCounter # Call C \n\
csrr t3,mtvec # Verify execption vector \n\
bne t3,zero,ok # Jump if not reset \n\
addi t4,t4,1 # Count zero vectors (fault) \n\

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