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Project housekeeping ...

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kaqu 9 months ago
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  1. 18
      README.md
  2. 7
      software/source/README.md
  3. 0
      software/source/fputest.c
  4. 0
      software/source/old/dramtransfer.c
  5. 0
      software/source/old/fpga2dram.c
  6. 0
      software/source/old/main.c
  7. 0
      software/source/old/my_vsnprintf.c
  8. 0
      software/source/old/risq5.c
  9. 0
      software/source/old/systime.c
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      software/source/testbranching1.c
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      software/source/testbranching2.c
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      software/source/testsoftinterrupts.c

18
README.md

@ -3,7 +3,8 @@
# Risq5 - one more clone to go ... #
This project demonstrates the use of LiteX & migen to create a full blown RISC-V CPU. The project requires a colorlight-5a-75b board (sells at ~18€ as of 10/2020).
This project demonstrates the use of LiteX & migen to create a full blown [RISC-V](https://en.wikipedia.org/wiki/RISC-V) CPU (RV32IMF). It shows a usually poorly documented IEEE 754 FPU logic implementation.
The project requires a colorlight-5a-75b board (minimum).
(Hint: project has been tested on Linux Mint 20 only, but should run on other Linux versions as well ...)
@ -42,6 +43,10 @@ https://blog.pcbxprt.com/index.php/2020/07/19/running-risc-v-core-on-small-fpga-
#### 3.1 General ####
The RISC-V ISA specification can be downloaded here:
[Vol. 1](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf)
& [Vol. 2](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf) (it'll probably help, to have these readily available ...).
The core consists of an L1 cache for program code loading (or L0 is it 🤔 ?), a 'data' load unit (LU) & the
corresponding store unit (SU), the base & FPU decoders as well as the data flow control logic (disturbingly called ALU - 🗣 respect the historical context!). The data flow is controllable via the Wishbone system bus
(even remotely!). All units are implemented w/ migen's finite state machines (FSMs).
@ -78,11 +83,12 @@ After installation of the relevant toolchains:
#### 3.4 Test assembly code ####
1. This time, open up a terminal & cd to the project local 'software' subdirectory
2. You can load an application to absolute location 0x40190000 (you may have to adjust local paths!):
./testloader.sh flwstw
./testloader.sh fputest
3. Run the debugger: risq5dbg.py with the same options as above (for risq5.py)
4. You're now able to verify correct operations of the cpu (well, hopefully 😎!)
### Some - maybe helpful - references for implementing IEEE 754 FPU logic: ###
### Some references concerning the implementation of IEEE 754 FPU logic: ###
- [IEEE 754 simulator](https://www.h-schmidt.net/FloatConverter/IEEE754.html)
- [IEEE 754 format usage](https://www.pitt.edu/~juy9/142/slides/L3-FP_Representation.pdf)
- [same as above](https://cs.boisestate.edu/~alark/cs354/lectures/ieee754.pdf)
@ -92,4 +98,10 @@ After installation of the relevant toolchains:
- [Floating point multiply & divide](https://wiki.eecs.yorku.ca/course_archive/2017-18/F/2021E/_media/chapter_3_add_mul.pdf)
- [Floating point division (video)](https://www.youtube.com/watch?v=fi8A4zz1d-s)
- [Methods of computing square roots](https://en.wikipedia.org/wiki/Methods_of_computing_square_roots)
### And for 'M' extension multiply/divide logic: ###
- [Bit-shifting tricks for integer multiply & divide](https://bisqwit.iki.fi/story/howto/bitmath/#DivAndModDivisionAndModulo)
### Disclaimer ###
This is a best effort project (& not even finished entirely!), no guarantees given. Things may or may not work ... so don't blame me if
somethin's screwed up! Relax 🧘 ! Improve 🏆 !

7
software/source/README.md

@ -1,7 +0,0 @@
main.c - This is the rudimentary BIOS loop
illumination.c - This is a sample application, demonstrating the use
of the 'neopixelengine' (the documentation can be found
under ./build/documentation/http/index.html)
dramtransfer.c - Testing async. DRAM access ...
my_vsnprintf.c - Some helpers. For float formatting use printf1() (really ugly!)
systime.c - (Daily) Time helper

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software/source/flwstw.c → software/source/fputest.c

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software/source/dramtransfer.c → software/source/old/dramtransfer.c

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software/source/fpga2dram.c → software/source/old/fpga2dram.c

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software/source/main.c → software/source/old/main.c

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software/source/my_vsnprintf.c → software/source/old/my_vsnprintf.c

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software/source/risq5.c → software/source/old/risq5.c

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software/source/systime.c → software/source/old/systime.c

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software/source/testbranching.c → software/source/testbranching1.c

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software/source/test1.c → software/source/testbranching2.c

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software/source/testinterrupts.c → software/source/testsoftinterrupts.c

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