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Still testing csr write (failing)

master
kaqu 2021-02-14 11:38:22 +01:00
parent 956d07c49d
commit 8891ac6964
3 changed files with 23 additions and 8 deletions
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10
debugger/qt5dbg.py
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@ -227,7 +227,7 @@ class dbgWindow(QMainWindow):
self.show()
self.timer = QTimer() # Start processing 'loop'
self.timer.setInterval(2000) # 2s for start ...
self.timer.setInterval(1000) # 1s update frequency
self.timer.setTimerType(Qt.PreciseTimer)
self.timer.timeout.connect(self.on_timer)
self.timer.start()
@ -263,12 +263,14 @@ class dbgWindow(QMainWindow):
self.qpbStatus.setText(msg)
i32FSMs = self.wb.regs.risq5_b32_FSMs.read()
msg = "FSMs: 0x{0:08X} (L1={1} ALU={2} LU={3} DECODE={4})".format(
msg = "FSMs: 0x{0:08X} (L1={1} ALU={2} LU={3} DECODE={4}) TIMER: mtime={5} mtimecmp={6}".format(
i32FSMs,
i32FSMs & 0xF,
(i32FSMs >> 4) & 0xF,
(i32FSMs >> 8) & 0xF,
(i32FSMs >> 12) & 0x1FF
(i32FSMs >> 12) & 0x1FF,
hex(self.wb.regs.clint_mtime.read()), # Timer/counter
hex(self.wb.regs.clint_mtimecmp.read()) # Timer limit
)
self.qpbFSMs.setText(msg)
@ -391,7 +393,7 @@ class dbgWindow(QMainWindow):
def on_clickTimerInt(self):
self.timer.stop()
print("*** TIMER INT RAISED ***")
self.wb.regs.clint_mtimecmp.write(self.wb.regs.clint_mtime.read()+0x400000) # Start timer
self.wb.regs.clint_mtimecmp.write(self.wb.regs.clint_mtime.read()+0x10000000) # Start timer
self.UpdateRISQ5Stati(True) # THE job
self.timer.start()

4
debugger/risq5dbg.py
View File

@ -27,8 +27,8 @@ def risq5dbg(csr_csv):
print("Entering single step mode")
wb.regs.risq5_b32mode.write(1) # Enable run (but will halt before 1. instruction!)
print("PC adjusted to 0x40190000")
wb.regs.risq5_b32_next_pc.write(0x40190550) # Provide a new PC address
print("PC adjusted to 0x40190078")
wb.regs.risq5_b32_next_pc.write(0x40190078) # Provide a new PC address
mode = wb.regs.risq5_b32mode.read() # Pick up current mode setting
wb.regs.risq5_b32mode.write(mode | 16) # Adjust PC, will load L1 2nd time now
wb.regs.risq5_b1_wb_reg_we.write(0) # Reset write requests (if any pending)

17
software/source/testtimerinterrupt.c
View File

@ -2,8 +2,18 @@
#pragma GCC diagnostic ignored "-Wunused-function"
static void setDownCounter(void)
{
clint_mtimecmp_write(clint_mtime_read()+0x100000); // Start timer
{ // 64-bit values!
//clint_mtimecmp_write(0x0000000010000000); //clint_mtime_read()+0x100000); // Start timer
//csr_write_simple(v >> 56, CSR_BASE + 0x6820L);
//csr_write_simple(v >> 48, CSR_BASE + 0x6824L);
//csr_write_simple(v >> 40, CSR_BASE + 0x6828L);
// csr_write_simple(v >> 32, CSR_BASE + 0x682cL); // 0x10
csr_write_simple(0x12, CSR_BASE + 0x682cL); // Just write delay
//csr_write_simple(v >> 24, CSR_BASE + 0x6830L);// 00
//csr_write_simple(v >> 16, CSR_BASE + 0x6834L);// 00
//csr_write_simple(v >> 8, CSR_BASE + 0x6838L); // 00
//csr_write_simple(v, CSR_BASE + 0x683cL);
}
#pragma GCC diagnostic ignored "-Wunused-function"
@ -13,6 +23,9 @@ static void start(void)
auipc ra,0 # Store current pc \n\
lui sp,%hi(0x40192000) # Setup stack pointer \n\
addi sp,sp,%lo(0x40192000) # s.a. \n\
addi t0,zero,123 # t0 = 123 \n\
sw t0,0(sp) # [0x40192000]=t0 \n\
lw t1,0(sp) # Reload test: t0=t1? \n\
nop # ... \n\
lui t0,%hi(myint) # Make interrupt vector known \n\
addi t0,t0,%lo(myint) # \n\