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Special CSRs (0xBC0/0xFC0) -> debugger

master
kaqu 2021-02-15 13:03:55 +01:00
parent 0cdd27d264
commit 80da8120ff
3 changed files with 12 additions and 8 deletions
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16
debugger/dbgeval.py
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@ -121,18 +121,22 @@ def disassemble(opcode, pc):
if f3 == 0x00:
msg = "jalr {0},{1}({2})".format(x_description[rd], hex(imm_i & 0xFFFFFFFF), x_description[rs1])
elif op == 0x73:
try:
csrname = csr_description[imm_i]
except:
csrname = "csr?{0}".format(hex(imm_i))
if f3 == 0x03: # csrrc rd, csr, rs1 (csr read & clear)
msg = "csrrc {0},{1},{2}".format(x_description[rd], csr_description[imm_i], x_description[rs1])
msg = "csrrc {0},{1},{2}".format(x_description[rd], csrname, x_description[rs1])
if f3 == 0x07: # csrrci rd, csr, imm_i4 (csr read & clear immediate)
msg = "csrrci {0},{1},{2}".format(x_description[rd], csr_description[imm_i], hex(rs1))
msg = "csrrci {0},{1},{2}".format(x_description[rd], csrname, hex(rs1))
if f3 == 0x02: # csrrs rd, csr, rs1 (csr read & set)
msg = "csrrs {0},{1},{2}".format(x_description[rd], csr_description[imm_i], x_description[rs1])
msg = "csrrs {0},{1},{2}".format(x_description[rd], csrname, x_description[rs1])
if f3 == 0x06: # csrrsi rd, csr, imm_i4 (csr read & set immediate)
msg = "csrrsi {0},{1},{2}".format(x_description[rd], csr_description[imm_i], hex(rs1))
msg = "csrrsi {0},{1},{2}".format(x_description[rd], csrname, hex(rs1))
if f3 == 0x01: # csrrw rd, csr, rs1 (csr read & write)
msg = "csrrw {0},{1},{2}".format(x_description[rd], csr_description[imm_i], x_description[rs1])
msg = "csrrw {0},{1},{2}".format(x_description[rd], csrname, x_description[rs1])
if f3 == 0x05: # csrrwi rd, csr, imm_i4 (csr read & write immediate)
msg = "csrrwi {0},{1},{2}".format(x_description[rd], csr_description[imm_i], hex(rs1))
msg = "csrrwi {0},{1},{2}".format(x_description[rd], csrname, hex(rs1))
if f3 == 0x00: # exception handling
if opcode == 0x30200073:
msg = "mret"

2
debugger/risq5dbg.py
View File

@ -25,7 +25,7 @@ def risq5dbg(csr_csv):
print("RISQ5 debugger started ...")
#print("Entering single step mode")
#wb.regs.risq5_b32mode.write(1) # Enable run (but will halt before 1. instruction!)
wb.regs.risq5_b32mode.write(1) # Enable run, L1 cache will load (but will halt before 1. instruction!)
#print("PC adjusted to 0x40190078")
#wb.regs.risq5_b32_next_pc.write(0x40190078) # Provide a new PC address

2
risq5.py
View File

@ -237,7 +237,7 @@ class BaseSoC(SoCCore):
self.add_csr("clint")
# Integrate my RISC-V cpu clone
RAMWAITTIME=32760 # 32-bit max. (8-bit 128 seems to work as well)
RAMWAITTIME=0x00100000 # 32-bit max. (8-bit 128 seems to work as well)
self.submodules.risq5 = risq5 = Risq5Core(
RAMWaitTime=RAMWAITTIME,
L1CacheSize=MAXWORDS,