fle.s/flt.s/feq.s ready

master
kaqu 1 year ago
parent 07396bd572
commit 64f19e9564
  1. 7
      debugger/dbgeval.py
  2. 49
      libmodules/fpu_decode.py
  3. 26
      libmodules/instruction_decode.py
  4. 4
      software/source/flwstw.c

@ -257,6 +257,13 @@ def disassemble(opcode, pc):
msg = "fmin.s {0},{1},{2}".format(f_description[rd], f_description[rs1], f_description[rs2])
elif f3 == 0x01:
msg = "fmax.s {0},{1},{2}".format(f_description[rd], f_description[rs1], f_description[rs2])
elif f7 == 0x50: # Compares
if f3 == 0x02:
msg = "feq.s {0},{1},{2}".format(x_description[rd], f_description[rs1], f_description[rs2])
elif f3 == 0x01:
msg = "flt.s {0},{1},{2}".format(x_description[rd], f_description[rs1], f_description[rs2])
else: # f3 == 0x00
msg = "fle.s {0},{1},{2}".format(x_description[rd], f_description[rs1], f_description[rs2])
elif f7 == 0x60: # To integer conversion
if rs2 == 0x00:
msg = "fcnv.w.s {0},{1}".format(x_description[rd], f_description[rs1])

@ -42,6 +42,8 @@ class Risq5FPUDecoder(Module):
self.fcvt_wu_s = Signal()
self.fcvt_s_w = Signal()
self.fcvt_s_wu = Signal()
self.flt = Signal()
self.fready = Signal() # Indicate ready
self.fwrite = Signal() # F-Extension: Do a write to a float register
@ -77,7 +79,7 @@ class Risq5FPUDecoder(Module):
NextValue(self.m1, Cat(0,0,0, regs.fs1[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
NextValue(self.m2, Cat(0,0,0, regs.fs2[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
NextState("FADD1")
).Elif((self.fmin | self.fmax | self.fmadd | self.fmsub | self.fnmadd | self.fnmsub | self.fmul | self.fdiv) & ~self.fready, # Triggers set & ready flag reset externally!
).Elif((self.fmin | self.fmax | self.fmadd | self.fmsub | self.fnmadd | self.fnmsub | self.fmul | self.fdiv | self.flt) & ~self.fready, # Triggers set & ready flag reset externally!
NextValue(self.sign1, regs.fs1[31]),
NextValue(self.sign2, regs.fs2[31]),
NextValue(self.e1, regs.fs1[23:31] - 127),
@ -90,6 +92,8 @@ class Risq5FPUDecoder(Module):
NextState("FMIN1"),
).Elif(self.fmax, # Maximum
NextState("FMAX1")
).Elif(self.flt, # Compare: less than
NextState("FLT1")
).Else( # Multiplication variants
NextState("FMUL1"),
)
@ -697,6 +701,49 @@ class Risq5FPUDecoder(Module):
)
# End of fcvt.s.w processing
FPU_fsm.act("FLT1",
# Simple sign compare ahead
If(self.sign1 ^ self.sign2, # // Sign mismatch? That's easy!
If(self.sign1, # frs1 negative (only)?
NextValue(regs.rd_wrport.dat_w, 1), # frs1 < frs2
).Else( # frs2 negative (only)
NextValue(regs.rd_wrport.dat_w, 0), # frs1 > frs2
)
).Else(
# Same sign: Compare exponents, then (maybe) mantissas
If(self.e1 < self.e2, # frs1 smaller (absolute number)?
If(self.sign1, # But in negative range?
NextValue(regs.rd_wrport.dat_w, 0), # frs1 > frs2
).Else( # Positive range
NextValue(regs.rd_wrport.dat_w, 1), # frs1 < frs2
)
).Elif(self.e2 < self.e1, # f2 smaller (absolute value)
If(self.sign1, # But f1 in negative range?
NextValue(regs.rd_wrport.dat_w, 1), # frs1 < frs2
).Else( # Positive
NextValue(regs.rd_wrport.dat_w, 0), # frs1 > frs2
)
).Else( # Equal exponents?
If(self.m1 < self.m2, # Compare mantissas: f1 smaller
If(self.sign1, # But negative?
NextValue(regs.rd_wrport.dat_w, 0), # frs1 > frs2
).Else( # Positive
NextValue(regs.rd_wrport.dat_w, 1), # frs1 < frs2
)
).Else( # f2 smaller/equal
If(self.sign1, # But negative?
NextValue(regs.rd_wrport.dat_w, 1), # frs1 < frs2
).Else( # Positive
NextValue(regs.rd_wrport.dat_w, 0), # frs1 > frs2
)
)
)
),
NextValue(writepost, 1), # Write required (but integer register)
NextValue(self.fready, 1), # Indicate ready to main decoder
NextState("FPU_IDLE")
)
if __name__ == "__main__":
print("***** Register file is passive ... ;) *****")

@ -368,12 +368,18 @@ class Risq5Decoder(Module):
NextValue(self.DECODE_state, 0x0F), # Dummy action
)
).Elif(regs.f7 == 0x50, # compares
If(regs.f3 == 0x02, # feq.s
NextValue(self.DECODE_state, 0x0F), # Dummy action
).Elif(regs.f3 == 0x01, # flt.s
NextValue(self.DECODE_state, 0x0F), # Dummy action
).Else( #regs.f3 == 0x00, # fle.s
NextValue(self.DECODE_state, 0x0F), # Dummy action
If(regs.f3 == 0x02, # feq.s rd, frs1, frs2
NextValue(regs.rd_wrport.dat_w, regs.fs1 == regs.fs2),
NextValue(writepost, 1), # Trigger write rd (x-reg)
).Elif(regs.f3 == 0x01, # flt.s rd, frs1, frs2
NextValue(fpu_decoder.flt, 1),
).Else( #regs.f3 == 0x00, # fle.s rd, frs1, frs2
If(regs.fs1 == regs.fs2,
NextValue(regs.rd_wrport.dat_w, 1),
NextValue(writepost, 1), # Trigger write rd (x-reg)
).Else(
NextValue(fpu_decoder.flt, 1),
)
)
).Elif(regs.f7 == 0x68, # fcvt.s
If(regs.rs2 == 0x00, # fcvt.s.w frd, rs1
@ -406,7 +412,10 @@ class Risq5Decoder(Module):
NextValue(self.next, 1), # Indicate ready state to ALU
NextState("DECODE_IDLE") # No write!
).Else(
If(fpu_decoder.fmadd | fpu_decoder.fmsub | fpu_decoder.fnmadd | fpu_decoder.fnmsub | fpu_decoder.fadd | fpu_decoder.fsub | fpu_decoder.fmul | fpu_decoder.fdiv | fpu_decoder.fsqrt | fpu_decoder.fmin | fpu_decoder.fmax | fpu_decoder.fcvt_w_s | fpu_decoder.fcvt_wu_s | fpu_decoder.fcvt_s_w | fpu_decoder.fcvt_s_wu, # FPU logic engaging?
If(fpu_decoder.fmadd | fpu_decoder.fmsub | fpu_decoder.fnmadd | fpu_decoder.fnmsub | fpu_decoder.fadd
| fpu_decoder.fsub | fpu_decoder.fmul | fpu_decoder.fdiv | fpu_decoder.fsqrt | fpu_decoder.fmin
| fpu_decoder.fmax | fpu_decoder.fcvt_w_s | fpu_decoder.fcvt_wu_s | fpu_decoder.fcvt_s_w | fpu_decoder.fcvt_s_wu
| fpu_decoder.flt, # FPU logic engaging?
NextState("FPU_WAIT") # Reset request within FPU_WAIT!
).Elif(self.div_instruction != 0, # M extension divide instruction?
If(regs.xs2s == 0x0, # RISC-V: Doesn't raise exception div/0!
@ -641,7 +650,8 @@ class Risq5Decoder(Module):
NextValue(fpu_decoder.fcvt_wu_s, 0),
NextValue(fpu_decoder.fcvt_s_w, 0),
NextValue(fpu_decoder.fcvt_s_wu, 0),
NextState("DECODE_WRITE")
NextValue(fpu_decoder.flt, 0),
NextState("DECODE_WRITE")
)
)

@ -6,6 +6,10 @@ static void start(void)
lui sp,%hi(0x40192000) # Setup stack pointer \n\
addi sp,sp,%lo(0x40192000) # s.a. \n\
repeat: fadd.s f2,f0,f1 # f2 = f0 + f1 \n\
feq.s x3,f0,f1 # x3 = (f0 == f1) \n\
flt.s x3,f0,f1 # x3 = (f0 < f1) \n\
fle.s x3,f0,f1 # x3 = (f0 < f1) \n\
j repeat # Loop ... \n\
fcvt.s.w f3,x3 # f3 = float((signed)x3) \n\
fcvt.s.wu f3,x3 # f3 = float((unsigned)x3) \n\
j repeat # Loop ... \n\

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