CSR regs access read fails (& write?), random ...

master
kaqu 2 years ago
parent ae8cab6a1e
commit 5ba92370ba
  1. 14
      debugger/dbgeval.py
  2. 5
      debugger/qt5dbg.py
  3. 7
      libmodules/core.py
  4. 6
      libmodules/instruction_decode.py
  5. 4
      risq5.py
  6. 5
      software/source/testtimerinterrupt.c

@ -118,7 +118,7 @@ def disassemble(opcode, pc):
elif op == 0x67: # I-Type (jalr)
if opcode == 0x00008067: # Special case: ret
msg = "ret ( jalr {0},{1}({2}) )".format(x_description[rd], hex(imm_i & 0xFFFFFFFF), x_description[rs1])
if f3 == 0x00:
elif f3 == 0x00:
msg = "jalr {0},{1}({2})".format(x_description[rd], hex(imm_i & 0xFFFFFFFF), x_description[rs1])
elif op == 0x73:
try:
@ -129,17 +129,17 @@ def disassemble(opcode, pc):
print("Special CSR detected: {0}".format(csrname))
if f3 == 0x03: # csrrc rd, csr, rs1 (csr read & clear)
msg = "csrrc {0},{1},{2}".format(x_description[rd], csrname, x_description[rs1])
if f3 == 0x07: # csrrci rd, csr, imm_i4 (csr read & clear immediate)
elif f3 == 0x07: # csrrci rd, csr, imm_i4 (csr read & clear immediate)
msg = "csrrci {0},{1},{2}".format(x_description[rd], csrname, hex(rs1))
if f3 == 0x02: # csrrs rd, csr, rs1 (csr read & set)
elif f3 == 0x02: # csrrs rd, csr, rs1 (csr read & set)
msg = "csrrs {0},{1},{2}".format(x_description[rd], csrname, x_description[rs1])
if f3 == 0x06: # csrrsi rd, csr, imm_i4 (csr read & set immediate)
elif f3 == 0x06: # csrrsi rd, csr, imm_i4 (csr read & set immediate)
msg = "csrrsi {0},{1},{2}".format(x_description[rd], csrname, hex(rs1))
if f3 == 0x01: # csrrw rd, csr, rs1 (csr read & write)
elif f3 == 0x01: # csrrw rd, csr, rs1 (csr read & write)
msg = "csrrw {0},{1},{2}".format(x_description[rd], csrname, x_description[rs1])
if f3 == 0x05: # csrrwi rd, csr, imm_i4 (csr read & write immediate)
elif f3 == 0x05: # csrrwi rd, csr, imm_i4 (csr read & write immediate)
msg = "csrrwi {0},{1},{2}".format(x_description[rd], csrname, hex(rs1))
if f3 == 0x00: # exception handling
elif f3 == 0x00: # exception handling
if opcode == 0x30200073:
msg = "mret"
elif opcode == 0x00100073:

@ -263,14 +263,15 @@ class dbgWindow(QMainWindow):
self.qpbStatus.setText(msg)
i32FSMs = self.wb.regs.risq5_b32_FSMs.read()
msg = "FSMs: 0x{0:08X} (L1={1} ALU={2} LU={3} DECODE={4}) TIMER: mtime={5} mtimecmp={6}".format(
msg = "FSMs: 0x{0:08X} (L1={1} ALU={2} LU={3} DECODE={4}) TIMER: mtime={5} mtimecmp={6} SYSTIME:{7}".format(
i32FSMs,
i32FSMs & 0xF,
(i32FSMs >> 4) & 0xF,
(i32FSMs >> 8) & 0xF,
(i32FSMs >> 12) & 0x1FF,
hex(self.wb.regs.clint_mtime.read()), # Timer/counter
hex(self.wb.regs.clint_mtimecmp.read()) # Timer limit
hex(self.wb.regs.clint_mtimecmp.read()), # Timer limit
hex(self.wb.regs.systime_b32CurrentMSeconds.read()) # Timer limit
)
self.qpbFSMs.setText(msg)

@ -59,7 +59,7 @@ class Risq5Core(Module, AutoCSR, AutoDoc, ModuleDoc):
:b32_FSMs: FSM states
"""
def __init__(self, RAMWaitTime=128, L1CacheSize=8, L1Cache=None, LUCacheSize=4, LUCache=None, SU_Unit=None, clint=None):
def __init__(self, RAMWaitTime=128, LU_CacheWait=24, L1CacheSize=8, L1Cache=None, LUCacheSize=4, LUCache=None, SU_Unit=None, clint=None):
# Inputs
self.b32mode = CSRStorage(32, reset_less=True,
@ -194,8 +194,7 @@ class Risq5Core(Module, AutoCSR, AutoDoc, ModuleDoc):
statusreg=self.b32status,
L1CacheOffset=self.L1CacheOffset,
L1CacheSize=L1CacheSize,
LUCacheOffset=self.LUCacheOffset,
LUCacheSize=LUCacheSize,
LU_CacheWait=LU_CacheWait, # May be as short as 24?!
LU_CacheValid=self.LU_CacheValid,
LUCache=LUCache,
SU_Unit=SU_Unit,
@ -263,7 +262,7 @@ class Risq5Core(Module, AutoCSR, AutoDoc, ModuleDoc):
self.submodules += ALU_fsm
self.ALU_state = Signal(4, reset_less=True) # Debugging support
self.ALU_loaddelay = Signal(32, reset_less=True) # 1st opcode load delay
self.ALU_loaddelay = Signal(32, reset_less=True) # 1st opcode load delay (TODO: shorter!)
ALU_fsm.act("ALU_INIT", # Initialize static registers (TODO: Run after reset?!)
NextValue(regs.csr[risq5defs.CSR_misa], 0x40000100), # misa: 32 bit/I 'extension'

@ -22,7 +22,7 @@ class Risq5Decoder(Module):
"""
Risq5 instruction decode phase logic
"""
def __init__(self, regs=None, modereg=None, statusreg=None, L1CacheOffset=None, L1CacheSize=32, L1_CacheValid=None, LUCacheOffset=None, LUCacheSize=4, LU_CacheValid=None, LUCache=None, SU_Unit=None):
def __init__(self, regs=None, modereg=None, statusreg=None, L1CacheOffset=None, L1CacheSize=32, LU_CacheWait=24, LU_CacheValid=None, LUCache=None, SU_Unit=None):
assert isinstance(regs, Risq5RegisterFile)
self.start = Signal() # Start decoding signal
@ -63,7 +63,7 @@ class Risq5Decoder(Module):
statusreg.storage[9].eq(self.L1BeyondI)
]
self.DECODE_loaddelay = Signal(8, reset_less=True) # Load unit cache data load delay
self.DECODE_loaddelay = Signal(32, reset_less=True) # TODO: shorter! Load unit cache data load delay (8-bit: 24 for RAM)
self.opcode_invalid = Signal(reset_less=True)
DECODE_fsm = FSM(reset_state="DECODE_IDLE") # FSM starts idling ...
@ -316,7 +316,7 @@ class Risq5Decoder(Module):
)
DECODE_fsm.act("DECODE_MEMWAIT2",
NextValue(self.DECODE_state,4),
If(self.DECODE_loaddelay > 24, # 24 ok (but why?)
If(self.DECODE_loaddelay > LU_CacheWait, # 24 ok (but why?)
If(regs.op == 0x23, # Actually for S-Type storing?
NextState("DECODE_PREPARESTORE") # Data now avail within LUCache.b32Data.storage
).Else(

@ -237,9 +237,11 @@ class BaseSoC(SoCCore):
self.add_csr("clint")
# Integrate my RISC-V cpu clone
RAMWAITTIME=0x00000200 # 32-bit max. for testing ... (TODO: 8-bit 128 seems to work as well)
RAMWAITTIME=128 # 32-bit max. for testing ... (TODO: 8-bit 128 seems to work as well)
LUWAITTIME=24
self.submodules.risq5 = risq5 = Risq5Core(
RAMWaitTime=RAMWAITTIME,
LU_CacheWait=LUWAITTIME,
L1CacheSize=MAXWORDS,
L1Cache=dramtransfer,
LUCacheSize=MAXMEMWORDS,

@ -10,7 +10,7 @@ extern uint32_t gettimer(void);
uint32_t gettimer(void)
{
uint32_t st = systime_b32CurrentMSeconds_read();
return st;
return st; // returend in a0
}
#pragma GCC diagnostic ignored "-Wunused-function"
@ -41,7 +41,8 @@ static void start(void)
loop: addi t0,t0,1 # Stupid job loop \n\
addi t0,t0,2 # ... \n\
add t2,zero,zero # Reset t2 \n\
call gettimer # Read systime clock \n\
call gettimer # Read systime clock (rc=a0) \n\
mv t5,a0 # Store reading \n\
j loop # Loop jump \n\
nop # \n\
myint: addi t1,t1,1 # Interrupt routine \n\

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