fsub/fmul ready
kaqu
parent
475617f9f7
commit
3c0d732020
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@ -228,6 +228,10 @@ def disassemble(opcode, pc):
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elif op == 0x53: # R-Type (F-Extension)
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if f7 == 0x00: # fadd
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msg = "fadd.s {0},{1},{2}".format(f_description[rd], f_description[rs1], f_description[rs2])
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elif f7 == 0x04: # fsub
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msg = "fsub.s {0},{1},{2}".format(f_description[rd], f_description[rs1], f_description[rs2])
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elif f7 == 0x08: # fmul
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msg = "fmul.s {0},{1},{2}".format(f_description[rd], f_description[rs1], f_description[rs2])
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elif f7 == 0x10: # sign injection/inverted/xor'ed
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if f3 == 0x00:
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msg = "fsgnj.s {0},{1},{2}".format(f_description[rd], f_description[rs1], f_description[rs2])
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@ -25,7 +25,10 @@ class Risq5FPUDecoder(Module):
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def __init__(self, regs=None):
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assert isinstance(regs, Risq5RegisterFile)
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self.fadd = Signal() # F-Extension: fadd job trigger
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# F-Extension: Job triggers
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self.fadd = Signal()
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self.fsub = Signal()
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self.fmul = Signal()
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self.fready = Signal() # Indicate ready
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self.fwrite = Signal() # F-Extension: Do a write to a float register
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@ -39,6 +42,7 @@ class Risq5FPUDecoder(Module):
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self.m1 = Signal((23+1+3,False), reset_less=True) # Unsigned mantissas! TODO: Verify sign!
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self.m2 = Signal((24+1+3,False), reset_less=True) # 23 bits + 1bit (1.xx = 0x800000)
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self.m3 = Signal((25+1+3,True), reset_less=True) # + Sign + R(0)/Guard & Sticky bits
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self.lm3 = Signal((64,True), reset_less=True) # MUL long result
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self.s_bit = Signal() # Sticky bit (for rounding control)
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self.branch1 = Signal() # Branch helpers
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self.branch2 = Signal()
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@ -49,14 +53,22 @@ class Risq5FPUDecoder(Module):
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FPU_fsm.act("FPU_IDLE",
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NextValue(self.FPU_state, 0),
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If(self.fadd & ~self.fready, # Triggers set & ready flag reset externally!
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NextValue(self.sign1, regs.fs1[31]),
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NextValue(self.sign2, regs.fs2[31]),
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If((self.fadd | self.fsub) & ~self.fready, # Triggers set & ready flag reset externally!
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NextValue(self.sign1, regs.fs1[31]),
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NextValue(self.sign2, regs.fs2[31] ^ self.fsub), # Invert sign for subtraction!
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NextValue(self.e1, regs.fs1[23:31] - 127),
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NextValue(self.e2, regs.fs2[23:31] - 127),
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NextValue(self.m1, Cat(0,0,0, regs.fs1[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
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NextValue(self.m2, Cat(0,0,0, regs.fs2[0:23], 1, 0)), # | 0x00800000 + R/G/S bits
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NextState("FADD1")
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).Elif(self.fmul & ~self.fready, # Triggers set & ready flag reset externally!
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NextValue(self.sign1, regs.fs1[31]),
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NextValue(self.sign2, regs.fs2[31]),
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NextValue(self.e1, regs.fs1[23:31] - 127),
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NextValue(self.e2, regs.fs2[23:31] - 127),
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NextValue(self.m1, Cat(regs.fs1[0:23], 1, 0)), # | 0x00800000
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NextValue(self.m2, Cat(regs.fs2[0:23], 1, 0)), # | 0x00800000
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NextState("FMUL1")
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)
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)
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@ -170,7 +182,7 @@ class Risq5FPUDecoder(Module):
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NextValue(self.m3, self.m3 + self.s_bit),
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NextState("FADD8") # Adjust possible overflow ...
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).Else( # Nope, all ready
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NextState("FADD9")
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NextState("FRESULT")
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)
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)
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)
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@ -180,9 +192,10 @@ class Risq5FPUDecoder(Module):
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NextValue(self.m3, self.m3 >> 1), # Adjust mantissa & increment exponent
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NextValue(self.e3, self.e3 + 1)
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),
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NextState("FADD9")
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)
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FPU_fsm.act("FADD9",
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NextState("FRESULT")
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) # End of fadd.s processing
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FPU_fsm.act("FRESULT", # Result contruction & possible rounding
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NextValue(self.FPU_state, 9),
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# 6. Build the actual resulting float
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NextValue(regs.frd_wrport.dat_w, Cat(self.m3[0:23], self.e3+127, self.sign3)),
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@ -197,7 +210,80 @@ class Risq5FPUDecoder(Module):
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NextValue(self.fwrite, 1), # Write required
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NextValue(self.fready, 1), # Indicate ready to main decoder
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NextState("FPU_IDLE")
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) # End of fadd.s processing
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)
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FPU_fsm.act("FMUL1",
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NextValue(self.FPU_state, 1),
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# 0. Verify valid ranges 1st!
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If(((regs.fs1 & 0x7FFFFFFF) == 0x7FFFFFFF) | ((regs.fs2 & 0x7FFFFFFF) == 0x7FFFFFFF),
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NextValue(regs.fcs, regs.fcs | 0x10), # NV: Invalid operation
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NextValue(regs.frd_wrport.dat_w, 0x7FFFFFFF), # NAN
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NextValue(self.fwrite, 1),
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NextValue(self.fready, 1),
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NextState("FPU_IDLE")
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).Elif(self.e1 == -1, # Infinity
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NextValue(regs.fcs, regs.fcs | 0x04), # OF: Overflow
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NextValue(regs.frd_wrport.dat_w, regs.fs1), # Return infinity
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NextValue(self.fwrite, 1),
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NextValue(self.fready, 1),
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NextState("FPU_IDLE")
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).Elif(self.e2 == -1, # Infinity
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NextValue(regs.fcs, regs.fcs | 0x04), # OF: Overflow
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NextValue(regs.frd_wrport.dat_w, regs.fs2), # Return infinity
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NextValue(self.fwrite, 1),
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NextValue(self.fready, 1),
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NextState("FPU_IDLE")
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).Else( # Ok, valid floats supplied ...
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NextValue(self.sign3, self.sign1 ^ self.sign2), # 1. Calculate result sign
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NextValue(self.e3, self.e1 + self.e2), # 2. Calculate resulting exponent (add!)
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NextValue(self.lm3, self.m1 * self.m2), # 3. Significants multiplication (result size: 2x (sizeof(mantissa)+1) !)
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NextState("FMUL2")
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)
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)
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FPU_fsm.act("FMUL2",
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NextValue(self.FPU_state, 2),
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# 4. MSB set in significants (i.e. bit[45])?
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# Bitoffset: 48 32 16 0
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If(self.lm3[47], # & 0x0000800000000000, TODO: Verify bit# (45 or 47?)!
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NextValue(self.lm3, self.lm3 >> 1), # Normalize result: Overflow
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NextValue(self.e3, self.e3 + 1),
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),
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If(self.fmul, # Regular multiplication
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NextState("FMUL3") # Do the rounding!
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).Else( # Fused multiply/add? W/O rounding!
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NextState("FMUL5")
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)
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)
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FPU_fsm.act("FMUL3",
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# 5. Rounding to nearest/even (FCS_FRM=0x00)
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If(self.lm3[22] & self.lm3[23], # & 0xC00000) == 0xC00000 Remainder (to be skipped): RESULTBIT(0) + REMAINDERBIT(MSB) set?
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If(self.lm3[0:22] != 0, # Sticky-Bit S (ORed rest) set?
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#Bit:48 32 16 0 (>>23)
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# 0000 2000 0000 0000 (Overflow 1.x)
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NextValue(self.lm3, (self.lm3 & 0x00007FFFFF800000) + 0x800000), # Add remainder
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NextState("FMUL4")
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).Else(
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NextState("FMUL5")
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)
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).Else(
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NextState("FMUL5")
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)
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)
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FPU_fsm.act("FMUL4",
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# Overflow normalization
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# Bit:48 32 16 0
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If(self.lm3[47], # & 0x0000800000000000
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NextValue(self.lm3, self.lm3 >> 1), # Normalize result: Overflow
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NextValue(self.e3, self.e3 + 1)
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),
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NextState("FMUL5")
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)
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FPU_fsm.act("FMUL5",
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# 6. Construction of result
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NextValue(self.m3, (self.lm3 >> 23) & 0x7FFFFF),
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# TODO: e3=se3 omitted ok?
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NextState("FRESULT")
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) # End of fmul.s processing
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if __name__ == "__main__":
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@ -91,9 +91,11 @@ class Risq5Decoder(Module):
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#NextValue(self.next, 0), # Indicate not yet there ... -> Reset @ top level!
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NextValue(self.start, 0), # Once!
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NextValue(self.write, 0), # Trigger write rd reset
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NextValue(fpu_decoder.fadd, 0), # F-Extension: fadd job trigger
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NextValue(fpu_decoder.fready, 0), # F-Extension: Clear ready indication
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NextValue(fpu_decoder.fwrite, 0), # F-Extension: Trigger write frd reset
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# F-Extension
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NextValue(fpu_decoder.fready, 0), # Clear ready indication
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NextValue(fpu_decoder.fwrite, 0), # Trigger write frd reset
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NextValue(self.SUStore, 0), # Trigger store rs2 reset
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NextValue(self.opcode_invalid, 0), # Reset invalid opcode indication
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NextValue(self.div_instruction, 0), # M extension divide instruction special
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@ -327,11 +329,11 @@ class Risq5Decoder(Module):
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NextValue(self.DECODE_state, 0x0F), # Dummy action
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).Elif(regs.op == 0x53, # R-Type
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If(regs.f7 == 0x00, # fadd.s frd, frs1, frs2
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NextValue(fpu_decoder.fadd, 1), # Indicate eval. queue!
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NextValue(fpu_decoder.fadd, 1), # Post fadd.s indication
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).Elif(regs.f7 == 0x04, # fsub.s
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NextValue(self.DECODE_state, 0x0F), # Dummy action
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NextValue(fpu_decoder.fsub, 1), # Post fsub.s indication
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).Elif(regs.f7 == 0x08, # fmul.s
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NextValue(self.DECODE_state, 0x0F), # Dummy action
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NextValue(fpu_decoder.fmul, 1), # Post fmul.s indication
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).Elif(regs.f7 == 0x0C, # fdiv.s
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NextValue(self.DECODE_state, 0x0F), # Dummy action
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).Elif(regs.f7 == 0x2C, # fsqrt.s
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@ -403,8 +405,8 @@ class Risq5Decoder(Module):
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NextValue(self.next, 1), # Indicate ready state to ALU
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NextState("DECODE_IDLE") # No write!
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).Else(
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If(fpu_decoder.fadd, # Branch helper: fadd logic engage (req. reset within FPU_WAIT)
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NextState("FPU_WAIT")
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If(fpu_decoder.fadd | fpu_decoder.fsub | fpu_decoder.fmul, # FPU logic engaging?
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NextState("FPU_WAIT") # Reset request within FPU_WAIT!
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).Elif(self.div_instruction != 0, # M extension divide instruction?
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If(regs.xs2s == 0x0, # RISC-V: Doesn't raise exception div/0!
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NextValue(statusreg.storage[12], 1), # Indicate division by zero (TODO: Remove later!)
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@ -622,7 +624,9 @@ class Risq5Decoder(Module):
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# F-Extension: Wait for FPU ready signals
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DECODE_fsm.act("FPU_WAIT",
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If(fpu_decoder.fready, # Wait for FPU decoder ready flag
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NextValue(fpu_decoder.fadd, 0), # Reset fadd job queue trigger (because of NFA reentry later!)
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NextValue(fpu_decoder.fadd, 0), # Reset job queue triggers (because of NFA reentry later!)
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NextValue(fpu_decoder.fsub, 0),
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NextValue(fpu_decoder.fmul, 0),
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NextState("DECODE_WRITE")
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)
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)
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@ -1,7 +1,7 @@
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#!/usr/bin/env python3
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#
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# risq5.py
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# risq5_imf.py
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#
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# This file has been derived from LiteX-Boards/colorlight_5b_75x.py
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# Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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@ -13,7 +13,7 @@
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#
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# History:
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# --------
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# 22.12.20/KQ Inital version
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# 22.12.20/KQ Initially derived version
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#
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# Build/Use ----------------------------------------------------------------------------------------
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# - 'python3 risq5.py --build --revision=7.0 --uart-name=crossover --with-etherbone --ip-address=192.168.1.20 --csr-csv=build/csr.csv'
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@ -5,7 +5,9 @@ static void start(void)
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auipc ra,0 # Store current pc \n\
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lui sp,%hi(0x40192000) # Setup stack pointer \n\
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addi sp,sp,%lo(0x40192000) # s.a. \n\
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repeat: fadd.s f2,f0,f1 # f2 = f0 + f1 (x1=Select/x2=rc) \n\
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repeat: fadd.s f2,f0,f1 # f2 = f0 + f1 \n\
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fsub.s f2,f0,f1 # f2 = f0 - f1 \n\
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fmul.s f2,f0,f1 # f2 = f0 * f1 \n\
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j repeat # Loop ... \n\
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lw x3,0(sp) # Load float from stack (test) \n\
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lw x3,4(sp) # Load float from stack (test) \n\
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