Invalid instruction detect corrected

master
kaqu 2 years ago
parent ea1d7ce120
commit 28e696bff3
  1. 10
      libmodules/core.py
  2. 8
      libmodules/instruction_decode.py
  3. 2
      software/source/testhardinterrupts.c

@ -187,6 +187,7 @@ class Risq5Core(Module, AutoCSR, AutoDoc, ModuleDoc):
self.LU_CacheValid = Signal() # Indicate loaded LU cache
self.sync += self.b32status.storage[5].eq(self.LU_CacheValid) # Indicate cache status to external world
# Integrate an instruction decoder
self.submodules.decoder = decoder = Risq5Decoder(
regs=regs,
modereg=self.b32mode,
@ -198,7 +199,7 @@ class Risq5Core(Module, AutoCSR, AutoDoc, ModuleDoc):
LU_CacheValid=self.LU_CacheValid,
LUCache=LUCache,
SU_Unit=SU_Unit,
) # Integrate a decoder
)
#---------------- L1 cache -------------------------------------------------------------
L1_fsm = FSM(reset_state="L1_IDLE") # FSM starts idling ...
@ -207,14 +208,9 @@ class Risq5Core(Module, AutoCSR, AutoDoc, ModuleDoc):
self.L1_state = Signal(4, reset_less=True) # Debugging support
L1_fsm.act("L1_IDLE", # If cache not valid fill it!
NextValue(self.L1_state, 0),
If(~self.L1_CacheValid & self.b32mode.storage[0], # Invalid cache & run enabled ...
#If((regs.pc & 0x0F) != 0, # Not 16-byte aligned?
If(~self.L1_CacheValid & self.b32mode.storage[0], # Invalid cache & run enabled ...
NextValue(L1Cache.b32Address.storage, regs.pc & 0xFFFFFFF0), # Current PC (aligned) dictates loading ...
NextValue(self.L1CacheOffset, ((regs.pc & 0x0F) >> 2)), # Adjust pointer (local reader), 4-byte width=32-bit
#).Else(
# NextValue(self.L1CacheOffset, 0), # Reset pointer (local reader)
# NextValue(L1Cache.b32Address.storage, regs.pc), # Current PC dictates loading ...
#),
NextState("L1_LOAD1")
)
)

@ -264,7 +264,9 @@ class Risq5Decoder(Module):
).Else( # Undecodeable operations
# Test for illegal instruction -> Illegal instruction trap/halt
NextValue(self.opcode_invalid, 1), # Set invalid opcode indication
NextValue(regs.pc, regs.pc - 4), # Stick to current instruction (i.e. compensate)!
NextValue(self.L1Reload, 1), # Enforce cache reload
NextValue(self.opcode_invalid, 1), # Set invalid opcode indication
),
NextState("DECODE_WRITE") # Make sure rd can be written (if nec.)
)
@ -272,9 +274,9 @@ class Risq5Decoder(Module):
DECODE_fsm.act("DECODE_WRITE",
NextValue(self.DECODE_state, 2),
If(self.opcode_invalid, # Invalid opcode detected?
NextValue(regs.csr[risq5defs.CSR_mcause], risq5defs.MCAUSE_ILLEGAL_INSTRUCTION),
#NextValue(regs.csr[risq5defs.CSR_mcause], risq5defs.MCAUSE_ILLEGAL_INSTRUCTION), # TODO: Make use of trap
NextValue(statusreg.storage[2], 1), # Indicate illegal instruction (TODO: Remove later!)
NextValue(modereg.storage[1], 0), # Reset 'no single stepping' flag! Thus halting ...
NextValue(modereg.storage[1], 0), # Reset 'no single stepping' flag! Thus halting ...
NextValue(self.next, 1), # Indicate ready state to ALU
NextState("DECODE_IDLE") # No write!
).Else(

@ -3,7 +3,7 @@ static void start(void)
{
__asm__ __volatile__ ("\
auipc ra,0 # Store current pc \n\
#.word 0xFFFFFFFF # Invalid opcode \n\
.word 0xFFFFFFFF # Invalid opcode \n\
lui t0,%hi(myint) # Make interrupt vector known \n\
addi t0,t0,%lo(myint) # \n\
csrw mtvec,t0 # Store actual address \n\

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