flw/fsw (101% resources already!)

master
kaqu 2 years ago
parent 5ff94901af
commit 24c02c7835
  1. 24
      libmodules/core.py
  2. 37
      libmodules/instruction_decode.py
  3. 6
      libmodules/register_file.py

@ -131,6 +131,15 @@ class Risq5Core(Module, AutoCSR, AutoDoc, ModuleDoc):
description="""
Write ``b32_wb_reg_value`` to register offset ``wb_reg_no``
""")
self.b1_wb_freg_we = CSRStorage(1, reset_less=True,
fields=[CSRField("wb_freg_we", size=1, description="*Field*: bit", values=[
("0", "DISABLED", "-"),
("1", "ENABLED", "WRITE"),
])
],
description="""
F-Extension: Write ``b32_wb_reg_value`` to float register offset ``wb_reg_no``
""")
# Outputs
self.b32_PC = CSRStorage(32, reset_less=True,
@ -143,6 +152,11 @@ class Risq5Core(Module, AutoCSR, AutoDoc, ModuleDoc):
description="""
Value of register index ``wb_reg_no``
""")
self.b32_wb_freg_value_r = CSRStorage(32, reset_less=True,
fields=[CSRField("wb_freg_value_r", size=32, description="*Field*: 32-Bit value")],
description="""
F-Extension: Value of float register index ``wb_reg_no``
""")
self.b32_FSMs = CSRStorage(32, reset_less=True,
fields=[
@ -175,6 +189,12 @@ class Risq5Core(Module, AutoCSR, AutoDoc, ModuleDoc):
regs.ext_wrport.dat_w.eq(self.b32_wb_reg_value_w.storage), # & value as well ...
regs.ext_wrport.we.eq(self.b1_wb_reg_we.storage) # Write request (pulse) forwarder
]
self.sync += [ # F-Extension: External register file write port (debugger)
regs.fwrite_ext_index.eq(self.b5_wb_reg_no.storage), # Let write index follow
regs.fext_wrport.dat_w.eq(self.b32_wb_reg_value_w.storage), # & value as well ...
regs.fext_wrport.we.eq(self.b1_wb_freg_we.storage) # Write request (pulse) forwarder
]
# Instruction fetch ------------------------------------------------------------------------
self.L1CacheOffset = Signal(9) # 0..511 log2_int(L1CacheSize, False)) # Cache reading offset (0..(Size-1))=>Bits)
self.sync += L1Cache.b9Offset.storage.eq(self.L1CacheOffset) # Index cache for reading (forwarded)
@ -377,11 +397,13 @@ class Risq5Core(Module, AutoCSR, AutoDoc, ModuleDoc):
)
self.comb += [
regs.read_ext_index.eq(self.b5_wb_reg_no.storage) # Relay external register read access
regs.read_ext_index.eq(self.b5_wb_reg_no.storage), # Relay external register read access
regs.fread_ext_index.eq(self.b5_wb_reg_no.storage) # F-Extension: External float register read access
]
self.sync += [ # Debugging support, indicate states & regs to outside world ...
self.b32_PC.storage.eq(regs.pc), # PC
self.b32_wb_reg_value_r.storage.eq(regs.ext_x), # Reg[index]
self.b32_wb_freg_value_r.storage.eq(regs.ext_f), # FReg[index]
self.b32_opcode.storage.eq(regs.opcode), # Next opcode to execute
self.b32_Counters.storage[16:25].eq(self.L1CacheOffset), # C#3 L1 cache offset (9-bit!)
self.b32status.storage[1].eq(self.b32_breakpoint.storage == regs.pc), # Breakpoint reached flag

@ -33,6 +33,7 @@ class Risq5Decoder(Module):
self.SUStore = Signal() # Signal SU to store a value
self.SUByteID = Signal(3, reset_less=True) # Uneven adressing remainder (0..3=byte, 4..5=halfword, 6=not used/direct write)
self.write = Signal() # Do a write (local register)
self.fwrite = Signal() # F-Extension: Do a write to a float register
self.L1Below = Signal(reset_less=True)
self.L1Beyond = Signal(reset_less=True) # Local cache boundaries (only valid w/ branches!)
@ -83,7 +84,8 @@ class Risq5Decoder(Module):
If(self.start, # Do the job when triggered
#NextValue(self.next, 0), # Indicate not yet there ... -> Reset @ top level!
NextValue(self.start, 0), # Once!
NextValue(self.write, 0), # Trigger write rd reset
NextValue(self.write, 0), # Trigger write rd reset
NextValue(self.fwrite, 0), # F-Extension: Trigger write frd reset
NextValue(self.SUStore, 0), # Trigger store rs2 reset
NextValue(self.opcode_invalid, 0), # Reset invalid opcode indication
NextValue(self.div_instruction, 0), # M extension divide instruction special
@ -298,10 +300,15 @@ class Risq5Decoder(Module):
),
#)
#------------------- F-Extension ----------------------------------------------------
).Elif(regs.op == 0x07, # I-Type: flw
NextValue(self.DECODE_state, 0x0F), # Dummy action
).Elif(regs.op == 0x27, # S-Type: fsw
NextValue(self.DECODE_state, 0x0F), # Dummy action
).Elif(regs.op == 0x07, # I-Type: flw frd, imm_offset(xs1)
NextValue(regs.LUAddress, regs.xs1u + regs.imm_i), # Calculate memory address: [rs1]+offset
NextValue(self.LUByteID, 7), # Type: Word (6->7!)
NextValue(self.LUReload, 1), # Enforce cache reload (for now: allways! TODO: Separate?)
).Elif(regs.op == 0x27, # S-Type: fsw frs2, imm_offset(xs1)
NextValue(SU_Unit.b32Address.storage, regs.xs1u + regs.imm_s), # Adjust DRAM target address
NextValue(SU_Unit.bData, regs.frs2), # Pick actual value to store (from fs2) & load SU
NextValue(self.SUByteID, 7), # Type: Word (6->7!)
NextValue(self.SUStore, 1), # Enforce store unit engagement (for now: allways!)
).Elif(regs.op == 0x43, # R4-Type: fmadd.s
NextValue(self.DECODE_state, 0x0F), # Dummy action
).Elif(regs.op == 0x47, # R4-Type: fmsub.s
@ -426,13 +433,19 @@ class Risq5Decoder(Module):
).Else( # No load no more ...
If(self.write & (regs.rd != 0), # Do NOT write to X0 (never! period!)
NextValue(regs.rd_wrport.we, 1), # Write value enable (delayed)
).Elif(self.fwrite, # F-Extension: frd write
NextValue(regs.frd_wrport.we, 1), # Write float value enable (delayed)
),
NextState("DECODE_READY") # Have register write being processed before continuing ...
)
)
)
DECODE_fsm.act("DECODE_READY",
NextValue(regs.rd_wrport.we, 0), # Kill WE enable!
If(self.fwrite, # F-Extension write to frd?
NextValue(regs.frd_wrport.we, 0), # Kill float WE enable!
).Else( # Normal write to rd!
NextValue(regs.rd_wrport.we, 0), # Kill WE enable!
),
NextState("DECODE_READY2")
)
DECODE_fsm.act("DECODE_READY2",
@ -452,13 +465,15 @@ class Risq5Decoder(Module):
DECODE_fsm.act("DECODE_MEMWAIT2",
NextValue(self.DECODE_state,4),
If(self.DECODE_loaddelay > LU_CacheWait, # 24 ok (but why?)
If(regs.op == 0x23, # Actually for S-Type storing?
If((regs.op == 0x23) | (regs.op == 0x27), # Actually for S-Type storing? (sw/F-Extension:fsw)
NextState("DECODE_PREPARESTORE") # Data now avail within LUCache.b32Data.storage
).Else(
If(self.LUByteID > 5, # No byte selection, 32-bit word type!
If(regs.op == 0x23, # Actually for S-Type storing?
NextState("DECODE_PREPARESTORE") # Data now avail within LUCache.b32Data.storage
).Else(
#If((regs.op == 0x23) | (regs.op == 0x27), # Actually for S-Type storing? (sw/F-Extension:fsw)
# NextState("DECODE_PREPARESTORE") # Data now avail within LUCache.b32Data.storage
If(regs.op == 0x07, # F-Extension: flw
NextValue(regs.frd_wrport.dat_w, LUCache.b32Data.storage), # Load actual value for xd (rd index already set)
).Else( # lw
NextValue(regs.rd_wrport.dat_w, LUCache.b32Data.storage), # Load actual value for xd (rd index already set)
)
).Elif(self.LUByteID == 0, # Byte 0
@ -520,7 +535,7 @@ class Risq5Decoder(Module):
).Elif(self.SUByteID == 5, # Half word high
NextValue(SU_Unit.bData, (LUCache.b32Data.storage & 0x0000FFFF) | (regs.xs2u[0:16] << 16)),
),
# Type 6 omitted (can be written straight forward=faster!)
# Type 6/7 (word/32-bit) omitted (can be written straight forward=faster!)
NextValue(self.SUStore, 1), # Enforce store unit engagement (for now: allways!)
NextState("DECODE_WRITE") # Start writing value
),

@ -79,6 +79,8 @@ class Risq5RegisterFile(Module):
self.rd_mul64su = Signal((64,True), reset_less=True) # M extension multiply result (signed x unsigned)
self.ext_x = Signal(32, reset_less=True) # Value to be read externally
self.ext_f = Signal(32, reset_less=True) # F-Extension: Float value to be read externally
self.LUAddress = Signal(32, reset_less=True) # Load unit address to use
self.SUAddress = Signal(32, reset_less=True) # Store unit address to use
@ -162,8 +164,8 @@ class Risq5RegisterFile(Module):
self.frs2.eq(frs2_rdport.dat_r),
frs3_rdport.adr.eq(self.frs3), # Read source register #3
self.frs3.eq(frs3_rdport.dat_r),
fext_rdport.adr.eq(self.fread_ext_index), # Read from external
self.fwrite_ext_index.eq(fext_rdport.dat_r),
fext_rdport.adr.eq(self.fread_ext_index), # Read from external
self.ext_f.eq(fext_rdport.dat_r),
]
# ------------------------- CSRs ----------------------------------------------------

Loading…
Cancel
Save