fcvt.s.w/fcvt.s.wu ready

master
kaqu 2 years ago
parent 8d0d848861
commit 07396bd572
  1. 7
      debugger/dbgeval.py
  2. 44
      libmodules/fpu_decode.py
  3. 14
      libmodules/instruction_decode.py
  4. 3
      software/source/flwstw.c

@ -257,11 +257,16 @@ def disassemble(opcode, pc):
msg = "fmin.s {0},{1},{2}".format(f_description[rd], f_description[rs1], f_description[rs2])
elif f3 == 0x01:
msg = "fmax.s {0},{1},{2}".format(f_description[rd], f_description[rs1], f_description[rs2])
elif f7 == 0x60: # integer conversion
elif f7 == 0x60: # To integer conversion
if rs2 == 0x00:
msg = "fcnv.w.s {0},{1}".format(x_description[rd], f_description[rs1])
else:
msg = "fcnv.wu.s {0},{1}".format(x_description[rd], f_description[rs1])
elif f7 == 0x68: # From integer conversion
if rs2 == 0x00:
msg = "fcnv.s.w {0},{1}".format(f_description[rd], x_description[rs1])
else:
msg = "fcnv.s.wu {0},{1}".format(f_description[rd], x_description[rs1])
elif f7 == 0x70:
if f3 == 0x00:
msg = "fmv.x.s {0},{1}".format(x_description[rd], f_description[rs1])

@ -40,6 +40,8 @@ class Risq5FPUDecoder(Module):
self.fmax = Signal()
self.fcvt_w_s = Signal()
self.fcvt_wu_s = Signal()
self.fcvt_s_w = Signal()
self.fcvt_s_wu = Signal()
self.fready = Signal() # Indicate ready
self.fwrite = Signal() # F-Extension: Do a write to a float register
@ -101,6 +103,17 @@ class Risq5FPUDecoder(Module):
NextValue(self.m1, Cat(regs.fs1[0:23], 0, 0)), # W/o 0x00800000 !
NextState("FCVT_W_S1")
)
).Elif((self.fcvt_s_w | self.fcvt_s_wu) & ~self.fready, # Trigger set & ready flag reset externally!
If(regs.xs1s[31] & self.fcvt_s_w, # Invert negative
NextValue(self.lm3, Cat(-regs.xs1s, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0)),
NextValue(self.sign3, 1), # & keep sign!
).Else( # Positive & unsigned type
NextValue(self.lm3, Cat( regs.xs1u, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0)),
NextValue(self.sign3, 0), # Positive anyway!
),
NextValue(self.m3, 0), # Init. vals.
NextValue(self.e3, 127),
NextState("FCVT_S_W1")
)
)
@ -256,7 +269,7 @@ class Risq5FPUDecoder(Module):
# 6. Build the actual resulting float
NextValue(regs.frd_wrport.dat_w, Cat(self.m3[0:23], self.e3+127, self.sign3)),
If((self.m3[0:23] != 0) | ((self.e3+127) != 0), # Not zero?
If(self.e3+127 == 1, # FLT_MIN range
If((self.e3 + 127) == 1, # FLT_MIN range
NextValue(regs.fcs, regs.fcs | 0x02), # UF: Underflow
If(regs.fcs[5:8] == 0x01, # RTZ rounding
NextValue(regs.frd_wrport.dat_w, 0), # FLT_MIN -> Round to zero -> 0.0!
@ -655,6 +668,35 @@ class Risq5FPUDecoder(Module):
)
# End of fcvt.w.s processing
FPU_fsm.act("FCVT_S_W1",
If(self.lm3 >= 2,
# self.lm3 = oldsum
NextValue(self.s32, (self.lm3 >> 1)[0:32]), # s32 = sum = oldsum/2
NextState("FCVT_S_W2")
).Else(
NextValue(self.e3, self.e3 - 127), # Adjust to normal exponent
NextState("FRESULT") # before output
)
)
FPU_fsm.act("FCVT_S_W2",
If(self.s32 != 0, # 0 not reached? (Att.: Processes parallel to last line in block!)
##NextValue(self.m3, self.m3 >> 1),
# oldsum - (sum * 2)
If((self.lm3 - (self.s32 << 1)) != 0, # Remainder? PREVIOUS value - next value (parallel, s.a.!)
NextValue(self.m3, (self.m3 >> 1) | 0x400000)
).Else(
NextValue(self.m3, self.m3 >> 1),
),
NextValue(self.e3, self.e3 + 1),
NextValue(self.lm3, self.s32), # oldsum = sum
NextState("FCVT_S_W1")
).Else( # Zero reached: Pre-mature exit
NextValue(self.e3, self.e3 - 127),
NextState("FRESULT")
)
)
# End of fcvt.s.w processing
if __name__ == "__main__":
print("***** Register file is passive ... ;) *****")

@ -376,10 +376,10 @@ class Risq5Decoder(Module):
NextValue(self.DECODE_state, 0x0F), # Dummy action
)
).Elif(regs.f7 == 0x68, # fcvt.s
If(regs.rs2 == 0x00, # fcvt.s.w
NextValue(self.DECODE_state, 0x0F), # Dummy action
).Else( #regs.rs2 == 0x01, # fcvt.s.wu
NextValue(self.DECODE_state, 0x0F), # Dummy action
If(regs.rs2 == 0x00, # fcvt.s.w frd, rs1
NextValue(fpu_decoder.fcvt_s_w, 1)
).Else( #regs.rs2 == 0x01, # fcvt.s.wu frd, rs1
NextValue(fpu_decoder.fcvt_s_wu, 1)
)
).Else( # regs.f7 == 0x78, # fmv.s.x frd, rs1 (x-reg -> f-reg) FIXME: Not working?
NextValue(regs.frd_wrport.dat_w, regs.xs1u),
@ -406,7 +406,7 @@ class Risq5Decoder(Module):
NextValue(self.next, 1), # Indicate ready state to ALU
NextState("DECODE_IDLE") # No write!
).Else(
If(fpu_decoder.fmadd | fpu_decoder.fmsub | fpu_decoder.fnmadd | fpu_decoder.fnmsub | fpu_decoder.fadd | fpu_decoder.fsub | fpu_decoder.fmul | fpu_decoder.fdiv | fpu_decoder.fsqrt | fpu_decoder.fmin | fpu_decoder.fmax | fpu_decoder.fcvt_w_s | fpu_decoder.fcvt_wu_s, # FPU logic engaging?
If(fpu_decoder.fmadd | fpu_decoder.fmsub | fpu_decoder.fnmadd | fpu_decoder.fnmsub | fpu_decoder.fadd | fpu_decoder.fsub | fpu_decoder.fmul | fpu_decoder.fdiv | fpu_decoder.fsqrt | fpu_decoder.fmin | fpu_decoder.fmax | fpu_decoder.fcvt_w_s | fpu_decoder.fcvt_wu_s | fpu_decoder.fcvt_s_w | fpu_decoder.fcvt_s_wu, # FPU logic engaging?
NextState("FPU_WAIT") # Reset request within FPU_WAIT!
).Elif(self.div_instruction != 0, # M extension divide instruction?
If(regs.xs2s == 0x0, # RISC-V: Doesn't raise exception div/0!
@ -639,7 +639,9 @@ class Risq5Decoder(Module):
NextValue(fpu_decoder.fmax, 0),
NextValue(fpu_decoder.fcvt_w_s, 0),
NextValue(fpu_decoder.fcvt_wu_s, 0),
NextState("DECODE_WRITE")
NextValue(fpu_decoder.fcvt_s_w, 0),
NextValue(fpu_decoder.fcvt_s_wu, 0),
NextState("DECODE_WRITE")
)
)

@ -6,6 +6,9 @@ static void start(void)
lui sp,%hi(0x40192000) # Setup stack pointer \n\
addi sp,sp,%lo(0x40192000) # s.a. \n\
repeat: fadd.s f2,f0,f1 # f2 = f0 + f1 \n\
fcvt.s.w f3,x3 # f3 = float((signed)x3) \n\
fcvt.s.wu f3,x3 # f3 = float((unsigned)x3) \n\
j repeat # Loop ... \n\
fcvt.w.s x3,f3 # x3 = int(f3) \n\
fcvt.wu.s x3,f3 # x3 = uint(f3) \n\
j repeat # Loop ... \n\

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