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ROM integrated but not readable (yet)?!

master
kaqu 2021-02-24 18:09:05 +01:00
parent 0ea3ef07ee
commit 0654612b46
3 changed files with 89 additions and 8 deletions
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78
litex/litex/soc/integration/builder.py
View File

@ -89,10 +89,15 @@ class Builder:
src_dir = os.path.join(soc_directory, "software", name)
self.software_packages.append((name, src_dir))
def get_gcc_flags(self, GCC_FLAGS):
flags = GCC_FLAGS["standard"]
flags += " -D__vexriscv__"
return flags
def _generate_includes(self):
os.makedirs(self.include_dir, exist_ok=True)
os.makedirs(self.generated_dir, exist_ok=True)
if self.soc.cpu_type not in [None, "zynq7000"]:
variables_contents = []
def define(k, v):
@ -122,6 +127,68 @@ class Builder:
write_to_file(
os.path.join(self.generated_dir, "regions.ld"),
export.get_linker_regions(self.soc.mem_regions))
elif self.soc.cpu_type in [None]: # 24.02.21/KQ Added
CPU_VARIANTS = {
"standard": "Risq5",
}
GCC_FLAGS = {
"standard": "-march=rv32im -mabi=ilp32",
}
self.soc.cpu.name = "vexriscv" #"risq5"
self.soc.cpu.human_name = "VexRiscv" #"Risq5"
self.soc.cpu.variants = CPU_VARIANTS
self.soc.cpu.data_width = 32
self.soc.cpu.endianness = "little"
from litex.soc.cores.cpu import CPU_GCC_TRIPLE_RISCV32
self.soc.cpu.gcc_triple = CPU_GCC_TRIPLE_RISCV32
self.soc.cpu.linker_output_format = "elf32-littleriscv"
self.soc.cpu.nop = "nop"
self.soc.cpu.gcc_flags = self.get_gcc_flags(GCC_FLAGS)
#self.soc.cpu.io_regions = {0x80000000: 0x80000000} # origin, length
# Add constants
#self.soc.add_config("CPU_TYPE", str("risq5"))
#self.soc.add_config("CPU_VARIANT", str("standard")
#self.soc.add_constant("CONFIG_CPU_HUMAN_NAME", str("Risq5"))
self.soc.add_constant("CONFIG_CPU_NOP", str("nop"))
#self.soc.add_constant("ROM_BASE", 0x00000000)
#self.soc.add_constant("ROM_SIZE", 0x00008000)
##ifndef ROM
##define ROM_BASE 0x00000000L
##define ROM_SIZE 0x00008000
variables_contents = []
def define(k, v):
variables_contents.append("{}={}\n".format(k, _makefile_escape(v)))
for k, v in export.get_cpu_mak(self.soc.cpu, self.compile_software):
if v is not None:
define(k, v)
variables_contents.remove("CPU_DIRECTORY=/home/kln/fpga/litex/litex/litex/soc/cores/cpu\n")
variables_contents.append("CPU_DIRECTORY=/home/kln/fpga/litex/litex/litex/soc/cores/cpu/risq5\n")
define(
"COMPILER_RT_DIRECTORY",
get_data_mod("software", "compiler_rt").data_location)
define("SOC_DIRECTORY", soc_directory) # Special shortcut
variables_contents.append("export BUILDINC_DIRECTORY\n")
define("BUILDINC_DIRECTORY", self.include_dir)
for name, src_dir in self.software_packages:
define(name.upper() + "_DIRECTORY", src_dir)
for bios_option in self.bios_options:
assert bios_option in ["TERM_NO_HIST", "TERM_MINI", "TERM_NO_COMPLETE"]
define(bios_option, "1")
write_to_file(
os.path.join(self.generated_dir, "variables.mak"),
"".join(variables_contents))
write_to_file(
os.path.join(self.generated_dir, "output_format.ld"),
export.get_linker_output_format(self.soc.cpu))
write_to_file(
os.path.join(self.generated_dir, "regions.ld"),
export.get_linker_regions(self.soc.mem_regions))
write_to_file(
os.path.join(self.generated_dir, "mem.h"),
@ -202,13 +269,20 @@ class Builder:
self._generate_includes()
self._generate_csr_map()
self._generate_mem_region_map()
if self.soc.cpu_type is not None:
if self.soc.cpu.use_rom:
if self.soc.cpu.use_rom:
self._prepare_rom_software()
self._generate_rom_software(not self.soc.integrated_rom_initialized)
if self.soc.integrated_rom_size and self.compile_software:
if not self.soc.integrated_rom_initialized:
self._initialize_rom_software()
else: # 24.02.21/KQ Added (we want a BIOS w/o internal cpu!)
self._prepare_rom_software()
self._generate_rom_software(not self.soc.integrated_rom_initialized)
if self.soc.integrated_rom_size and self.compile_software:
if not self.soc.integrated_rom_initialized:
self._initialize_rom_software()
if "run" not in kwargs:
kwargs["run"] = self.compile_gateware

9
litex/litex/soc/integration/soc.py
View File

@ -850,8 +850,11 @@ class SoC(Module):
# Update SoC with CPU constraints
for n, (origin, size) in enumerate(self.cpu.io_regions.items()):
self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False))
# 14.02.21/KQ removed self.mem_map.update(self.cpu.mem_map) # FIXME: Nec. for cpu=None
self.mem_map.update(self.cpu.mem_map) # TODO: connect missing?
# w/ cpu update memory map
if not isinstance(self.cpu, cpu.CPUNone): # 14.02.21/KQ removed self.mem_map.update(self.cpu.mem_map)
self.mem_map.update(self.cpu.mem_map) # TODO: connect missing?
# Add Bus Masters/CSR/IRQs
if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000)):
if reset_address is None:
@ -1193,7 +1196,7 @@ class LiteXSoC(SoC):
# Add SDRAM region
self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size))
# Add CPU's direct memory buses (if not already declared) ----------------------------------
if hasattr(self.cpu, "add_memory_buses"):
self.cpu.add_memory_buses(

10
risq5_wo_vex.py
View File

@ -159,7 +159,11 @@ class BaseSoC(SoCCore):
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = True
)
# 24.02.21/KQ Intergrating ROM separately
from litex.soc.integration.soc import SoCRegion
self.bus.add_region("rom", SoCRegion(origin=0, size=0x00008000))
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
@ -175,8 +179,8 @@ class BaseSoC(SoCCore):
mac_address = mac_address,
)
# FIXME: Added 2nd master to csr (after master0)
##from litex.soc.interconnect import wishbone
##self.csr.add_master(name="cpu2csr", master=wishbone.Interface(8,14))
from litex.soc.interconnect import wishbone
self.csr.add_master(name="cpu2csr", master=wishbone.Interface(8,14))
#from litex.soc.interconnect import wishbone
#self.cpu2csr = cpu2csr = wishbone.Interface()
# Signals: ack, adr(14), bte(2), cti(3), cyc, dat_r(8), dat_w(8), err, sel, stb, we