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Fixed zero operand problems (hopefully!)

master
kaqu 9 months ago
parent
commit
01818b44a4
  1. 46
      libmodules/fpu_decode.py
  2. 15
      software/source/old/my_vsnprintf.c

46
libmodules/fpu_decode.py

@ -162,22 +162,31 @@ class Risq5FPUDecoder(Module):
NextValue(regs.frd_wrport.dat_w, regs.fs3 ^ 0x80000000), # Invert sign
).Elif(self.fmadd, # 0*x=>0! 0+fs3 = fs3!
NextValue(regs.frd_wrport.dat_w, regs.fs3), # Ready!
).Else( # Straight add
).Else( # Straight add (& fnmsub: -*- = +!)
NextValue(regs.frd_wrport.dat_w, regs.fs2), # Ready!
),
NextValue(self.fwrite, 1),
NextValue(self.fready, 1),
NextState("FPU_IDLE")
).Elif((self.fadd | self.fsub) & (regs.fs2[0:31] == 0), # Nothing to add? (w/o sign!)
NextValue(regs.frd_wrport.dat_w, regs.fs1), # Ready!
NextState("FPU_IDLE")
).Elif(self.fs2[0:31] == 0, # x+0: Nothing to add? (w/o sign!)
If(self.fnmadd | self.fnmsub,
NextValue(regs.frd_wrport.dat_w, self.fs1 ^ 0x80000000), # Ready!
).Else(
NextValue(regs.frd_wrport.dat_w, self.fs1), # Ready!
),
NextValue(self.fwrite, 1),
NextValue(self.fready, 1),
NextState("FPU_IDLE")
).Elif((self.fmadd | self.fmsub | self.fnmadd | self.fnmsub) & ((self.e2 == 0) & (self.m2 == 0)), # Nothing to add (w/o sign!)
If(self.fnmadd | self.fnmsub, # sign3/e3/m3 used in FRESULT
NextValue(self.sign3, ~self.sign3) # Invert result finally
),
NextState("FRESULT") # Just supply (normalized finally!) result from multiplication!
NextState("FPU_IDLE")
#).Elif((self.fadd | self.fsub) & (regs.fs2[0:31] == 0), # Nothing to add? (w/o sign!)
# NextValue(regs.frd_wrport.dat_w, regs.fs1), # Ready!
# NextValue(self.fwrite, 1),
# NextValue(self.fready, 1),
# NextState("FPU_IDLE")
#).Elif((self.fmadd | self.fmsub | self.fnmadd | self.fnmsub) & ((self.e2 == 0) & (self.m2 == 0)), # Nothing to add (w/o sign!)
# If(self.fnmadd | self.fnmsub, # sign3/e3/m3 used in FRESULT
# NextValue(self.sign3, ~self.sign3) # Invert result finally
# ),
# NextState("FRESULT") # Just supply (normalized finally!) result from multiplication!
).Else( # Ok, valid floats supplied ...
NextValue(self.s_bit, 0),
NextValue(self.branch1, 0), # Reset helpers
@ -333,10 +342,17 @@ class Risq5FPUDecoder(Module):
NextValue(self.fready, 1),
NextState("FPU_IDLE")
).Elif((regs.fs1[0:31] == 0) | (regs.fs2[0:31] == 0), # Nothing to multiply? (w/o sign!)
NextValue(regs.frd_wrport.dat_w, 0), # Result will be zero ...
NextValue(self.fwrite, 1),
NextValue(self.fready, 1),
NextState("FPU_IDLE")
If(self.fmul, # Single instruction? Straight return.
NextValue(regs.frd_wrport.dat_w, 0), # Result will be zero ...
NextValue(self.fwrite, 1),
NextValue(self.fready, 1),
NextState("FPU_IDLE")
).Else( # Fused instructions? Continue w/ signed zero
NextValue(self.sign3, self.sign1 ^ self.sign2),
NextValue(self.e3, -127), # Not 0! Will be adjusted in FMADD1
NextValue(self.m3, 0),
NextState("FMADD1")
)
).Else( # Ok, valid floats supplied ...
NextValue(self.sign3, self.sign1 ^ self.sign2), # 1. Calculate result sign
NextValue(self.e3, self.e1 + self.e2), # 2. Calculate resulting exponent (add!)
@ -842,4 +858,4 @@ class Risq5FPUDecoder(Module):
if __name__ == "__main__":
print("***** Register file is passive ... ;) *****")
print("***** Register file is passive ... ;) *****")

15
software/source/old/my_vsnprintf.c

@ -417,8 +417,19 @@ void printf1(const char *fmt, float f1)
}
}
}
strncpy(fstr, fr, 5); // Copy format only
my_sprintf(outputstr, fstr, f1); // Eval separately ...
strncpy(fstr, fr, 5); // Copy format only
if(f1 != 0.0) // Fails w/ zero ?!
my_sprintf(outputstr, fstr, f1); // Eval separately ...
else { // Zero special treatment
int i;
for(i=0;i < (width-remainder)-1;i++)
outputstr[i] = ' ';
outputstr[i++] = '0';
outputstr[i++] = '.';
for(;i < width;i++)
outputstr[i] = '0';
outputstr[width] = '\0'; // Respect field width
}
outputstr[width] = '\0'; // Respect field width
char *rest = strchr(outputstr,'.');
if(rest != NULL)

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