kaqu
1 year ago
2 changed files with 267 additions and 3 deletions
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# |
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# This file is part of LiteDRAM. |
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# |
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# Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk> |
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# Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr> |
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# Copyright (c) 2018 John Sully <john@csquare.ca> |
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# Copyright (c) 2016 Tim 'mithro' Ansell <mithro@mithis.com> |
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# SPDX-License-Identifier: BSD-2-Clause |
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"""Direct Memory Access (DMA) reader and writer modules.""" |
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from migen import * |
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from litex.soc.interconnect.csr import * |
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from litex.soc.interconnect import stream |
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from litedram.common import LiteDRAMNativePort |
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from litedram.frontend.axi import LiteDRAMAXIPort |
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# LiteDRAMDMAReader -------------------------------------------------------------------------------- |
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class LiteDRAMDMAReader(Module, AutoCSR): |
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"""Read data from DRAM memory. |
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For every address written to the sink, one DRAM word will be produced on |
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the source. |
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Parameters |
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---------- |
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port : port |
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Port on the DRAM memory controller to read from (Native or AXI). |
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fifo_depth : int |
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How many request results the output FIFO can contain (and thus how many |
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read requests can be outstanding at once). |
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fifo_buffered : bool |
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Implement FIFO in Block Ram. |
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Attributes |
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---------- |
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sink : Record("address") |
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Sink for DRAM addresses to be read. |
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source : Record("data") |
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Source for DRAM word results from reading. |
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rsv_level: Signal() |
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FIFO reservation level counter |
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""" |
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def __init__(self, port, fifo_depth=16, fifo_buffered=False): |
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assert isinstance(port, (LiteDRAMNativePort, LiteDRAMAXIPort)) |
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self.port = port |
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self.sink = sink = stream.Endpoint([("address", port.address_width)]) |
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self.source = source = stream.Endpoint([("data", port.data_width)]) |
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# # # |
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# Native / AXI selection |
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is_native = isinstance(port, LiteDRAMNativePort) |
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is_axi = isinstance(port, LiteDRAMAXIPort) |
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if is_native: |
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(cmd, rdata) = port.cmd, port.rdata |
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elif is_axi: |
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(cmd, rdata) = port.ar, port.r |
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else: |
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raise NotImplementedError |
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# Request issuance ------------------------------------------------------------------------- |
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request_enable = Signal() |
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request_issued = Signal() |
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if is_native: |
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self.comb += cmd.we.eq(0) |
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self.comb += [ |
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cmd.addr.eq(sink.address), |
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cmd.valid.eq(sink.valid & request_enable), |
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sink.ready.eq(cmd.ready & request_enable), |
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request_issued.eq(cmd.valid & cmd.ready) |
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] |
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# FIFO reservation level counter ----------------------------------------------------------- |
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# incremented when data is planned to be queued |
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# decremented when data is dequeued |
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data_dequeued = Signal() |
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self.rsv_level = rsv_level = Signal(max=fifo_depth+1) |
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self.sync += [ |
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If(request_issued, |
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If(~data_dequeued, rsv_level.eq(self.rsv_level + 1)) |
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).Elif(data_dequeued, |
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rsv_level.eq(rsv_level - 1) |
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) |
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] |
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self.comb += request_enable.eq(rsv_level != fifo_depth) |
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# FIFO ------------------------------------------------------------------------------------- |
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fifo = stream.SyncFIFO([("data", port.data_width)], fifo_depth, fifo_buffered) |
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self.submodules += fifo |
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self.comb += [ |
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rdata.connect(fifo.sink, omit={"id", "resp"}), |
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fifo.source.connect(source), |
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data_dequeued.eq(source.valid & source.ready) |
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] |
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def add_csr(self): |
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self._base = CSRStorage(32) |
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self._length = CSRStorage(32) |
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self._start = CSR() |
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self._done = CSRStatus() |
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self._loop = CSRStorage() |
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# # # |
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shift = log2_int(self.port.data_width//8) |
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base = Signal(self.port.address_width) |
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offset = Signal(self.port.address_width) |
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length = Signal(self.port.address_width) |
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self.comb += [ |
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base.eq(self._base.storage[shift:]), |
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length.eq(self._length.storage[shift:]), |
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] |
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self.submodules.fsm = fsm = FSM(reset_state="IDLE") |
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fsm.act("IDLE", |
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self._done.status.eq(1), |
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If(self._start.re, |
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NextValue(offset, 0), |
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NextState("RUN"), |
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) |
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) |
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fsm.act("RUN", |
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self.sink.valid.eq(1), |
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self.sink.address.eq(base + offset), |
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If(self.sink.ready, |
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NextValue(offset, offset + 1), |
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If(offset == (length - 1), |
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If(self._loop.storage, |
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NextValue(offset, 0) |
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).Else( |
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NextState("IDLE") |
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) |
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) |
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) |
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) |
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# LiteDRAMDMAWriter -------------------------------------------------------------------------------- |
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class LiteDRAMDMAWriter(Module, AutoCSR): |
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"""Write data to DRAM memory. |
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Parameters |
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---------- |
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port : port |
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Port on the DRAM memory controller to write to (Native or AXI). |
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fifo_depth : int |
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How many requests the input FIFO can contain (and thus how many write |
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requests can be outstanding at once). |
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fifo_buffered : bool |
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Implement FIFO in Block Ram. |
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Attributes |
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---------- |
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sink : Record("address", "data") |
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Sink for DRAM addresses and DRAM data word to be written too. |
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""" |
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def __init__(self, port, fifo_depth=16, fifo_buffered=False): |
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assert isinstance(port, (LiteDRAMNativePort, LiteDRAMAXIPort)) |
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self.port = port |
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self.sink = sink = stream.Endpoint([("address", port.address_width), |
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("data", port.data_width)]) |
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# # # |
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# Native / AXI selection ------------------------------------------------------------------- |
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is_native = isinstance(port, LiteDRAMNativePort) |
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is_axi = isinstance(port, LiteDRAMAXIPort) |
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if is_native: |
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(cmd, wdata) = port.cmd, port.wdata |
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elif is_axi: |
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(cmd, wdata) = port.aw, port.w |
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else: |
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raise NotImplementedError |
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# FIFO ------------------------------------------------------------------------------------- |
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fifo = stream.SyncFIFO([("data", port.data_width)], fifo_depth, fifo_buffered) |
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self.submodules += fifo |
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if is_native: |
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self.comb += cmd.we.eq(1) |
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self.comb += [ |
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cmd.addr.eq(sink.address), |
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cmd.valid.eq(fifo.sink.ready & sink.valid), |
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sink.ready.eq(fifo.sink.ready & cmd.ready), |
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fifo.sink.valid.eq(sink.valid & cmd.ready), |
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fifo.sink.data.eq(sink.data) |
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] |
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if is_native: |
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self.comb += wdata.we.eq(2**(port.data_width//8)-1) |
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if is_axi: |
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self.comb += wdata.strb.eq(2**(port.data_width//8)-1) |
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self.comb += [ |
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wdata.valid.eq(fifo.source.valid), |
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fifo.source.ready.eq(wdata.ready), |
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wdata.data.eq(fifo.source.data) |
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] |
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def add_csr(self): |
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self._sink = self.sink |
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self.sink = stream.Endpoint([("data", self.port.data_width)]) |
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self._base = CSRStorage(32) |
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self._length = CSRStorage(32) |
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self._start = CSR() |
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self._done = CSRStatus() |
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self._loop = CSRStorage() |
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# # # |
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shift = log2_int(self.port.data_width//8) |
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base = Signal(self.port.address_width) |
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offset = Signal(self.port.address_width) |
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length = Signal(self.port.address_width) |
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self.comb += [ |
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base.eq(self._base.storage[shift:]), |
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length.eq(self._length.storage[shift:]), |
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] |
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self.submodules.fsm = fsm = FSM(reset_state="IDLE") |
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fsm.act("IDLE", |
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self._done.status.eq(1), |
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If(self._start.re, |
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NextValue(offset, 0), |
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NextState("RUN"), |
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) |
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) |
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fsm.act("RUN", |
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self._sink.valid.eq(self.sink.valid), |
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self._sink.data.eq(self.sink.data), |
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self._sink.address.eq(base + offset), |
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self.sink.ready.eq(self._sink.ready), |
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If(self.sink.valid & self.sink.ready, |
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NextValue(offset, offset + 1), |
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If(offset == (length - 1), |
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If(self._loop.storage, |
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NextValue(offset, 0) |
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).Else( |
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NextState("IDLE") |
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) |
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) |
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) |
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) |
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