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@ -56,9 +56,11 @@ from litex.soc.integration.soc_core import * |
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from litex.soc.integration.builder import * |
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage, CSRField |
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from litex.soc.interconnect.stream import SyncFIFO |
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from litedram.modules import M12L16161A, M12L64322A |
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY |
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from litedram.frontend.dma import LiteDRAMDMAReader, LiteDRAMDMAWriter |
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII |
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@ -67,8 +69,8 @@ from litex.build.generic_platform import * |
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import litex.soc.doc as lxsocdoc |
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# KQ's helper modules ... |
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from modules.systime import SysTime |
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from modules.dramtransfer import DRAMTransfer |
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from libmodules.systime import SysTime |
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from libmodules.dramtransfer import DRAMTransfer |
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from neopixelengine import NeoPixelEngine |
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@ -387,9 +389,19 @@ class BaseSoC(SoCCore): |
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self.submodules.systime = systime = SysTime(comparecount=0x0000EA90) |
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self.add_csr("systime") |
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# DRAM test |
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MAXWORDS = 32 # Transfer length x 32-bit, FIFO depth |
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self.submodules.mm2s = mm2s = LiteDRAMDMAReader(self.sdram.crossbar.get_port(), fifo_depth=MAXWORDS, fifo_buffered=True) |
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mm2s.add_csr() |
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self.add_csr("mm2s") |
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self.submodules.sync_fifo = sync_fifo = SyncFIFO([("data", 32)], MAXWORDS, True) |
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self.comb += mm2s.source.connect(sync_fifo.sink) # Connect DMA-Reader.source -> FIFO.sink |
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self.submodules.dramtransfer = DRAMTransfer(maxwords=MAXWORDS, dma_reader=mm2s, sync_fifo=sync_fifo) |
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self.add_csr("dramtransfer") |
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# Adjust no. for your actual project ... |
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max_TABLES = 3 # 1..16 |
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max_LEDS_per_chain = 27 # 1..256 |
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max_TABLES = 2 # 1..16 |
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max_LEDS_per_chain = MAXWORDS # 1..256 |
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self.submodules.npe = NeoPixelEngine(n_TABLES=max_TABLES, n_LEDs=max_LEDS_per_chain) |
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self.add_csr("npe") |
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for i in range(42,56+2): # Example: Do output on J4 (14) & J5 (2) |
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