1st LED included! But: Disable keeps it going?!

master
kaqu 2 years ago
parent 95a1b0fa9e
commit abf378b94a
  1. 12
      firmware/main.c
  2. 16
      neopixelar.py
  3. 34
      neopixelengine.py
  4. 43698
      npe.vcd

@ -70,8 +70,8 @@ static void boot_sequence(void)
//------------------- Illumination demo --------------------------------
extern void busy_wait(unsigned int ms);
#define MAXTABLES 3 // 16
#define MAXLEDS 27 // 256 MUST match h/w!
#define MAXTABLES 3 // 1..16 MUST match h/w!
#define MAXLEDS 27 // 1..256 MUST match h/w!
static int32_t arLEDBuffer[MAXTABLES][MAXLEDS]; // GRB values
void enable_LEDS(int iEnable)
@ -83,10 +83,10 @@ void enable_LEDS(int iEnable)
void send_LEDs()
{
for(int j=0;j<MAXTABLES;j++) {
npe_b4LoadTable_write(j);
npe_b4LoadTable_write(j); // Select table
for(int i=0;i<MAXLEDS;i++) {
npe_b8LoadOffset_write(i); // @Offset
npe_b24Data2Load_write(arLEDBuffer[j][i]); // store 32(24) bit value
npe_b8LoadOffset_write(i); // and offset
npe_b24Data2Load_write(arLEDBuffer[j][i]); // store 32(24) bit value @Table/Offset
}
}
busy_wait(25); // Minimum that meets the eye ;)
@ -107,7 +107,7 @@ void load_triple_LEDs(int iTable, int32_t green, int32_t red, int32_t blue)
}
}
void illumination()
void illumination(void)
{
int32_t green = 0x040000;
int32_t red = 0x000400;

@ -18,15 +18,13 @@
# 19.10.20/KQ Project renamed 'NeoPixelar' (swedish plural for NeoPixel ...)
#
# Build/Use ----------------------------------------------------------------------------------------
# - 'python3 neopixelar.py --build --revision=7.0 --uart-name=crossover --with-etherbone" --csr-csv=build/csr.csv'
# - 'python3 neopixelar.py --build --revision=7.0 --uart-name=crossover --with-etherbone --ip-address=192.168.1.20 --csr-csv=build/csr.csv'
# to generate
# - 'python3 neopixelar.py --load' to download to FPGA
# - 'ping 192.168.1.50' to verify ethernet connection - via LEFT(!) RJ45 port
# - 'ping 192.168.1.20' to verify ethernet connection - via LEFT(!) RJ45 port
# - 'wishbone-tool --ethernet-host 192.168.1.20 --server terminal --csr-csv build/csr.csv'
# You should see the LiteX BIOS and be able to interact with it
#
# ~/fpga/litex/litex/litex/soc/doc/module.py for autodoc functionality ...
#
import os
import argparse
import sys
@ -335,13 +333,11 @@ class BaseSoC(SoCCore):
platform.add_extension(_gpios) # General LED outputs
max_TABLES = 16
max_LEDS_per_chain = 256
max_TABLES = 16 # 1..16
max_LEDS_per_chain = 32 # 1..256
self.submodules.npe = NeoPixelEngine(n_TABLES=max_TABLES, n_LEDs=max_LEDS_per_chain)
self.add_csr("npe")
#self.comb += platform.request("gpio", 42).eq(self.npe.bDataPin[0]) # Output data pin
#self.comb += platform.request("gpio", 43).eq(self.npe.bDataPin[1]) # Output data pin
for i in range(42,56+2): # Do output on J4 42/43/44/45/46/47/48/49/50/51/52/53/54/55
self.add_csr("npe")
for i in range(42,56+2): # Do output on J4 (14) & J5 (2)
self.comb += platform.request("gpio", i).eq(self.npe.bDataPin[i-42]) # Output data pin
# Build --------------------------------------------------------------------------------------------

@ -15,6 +15,7 @@
# 18.10.20/KQ Cleanup & more 'array'
# 19.10.20/KQ Renamed from 'neopixelprotocol'
# 27.10.20/KQ Using AutoDoc etc(improved documentation generation)
# 29.10.20/KQ Memory object replaces array (due to resource consumption)
#
from migen import *
@ -60,11 +61,8 @@ class NeoPixelEngine(Module, AutoCSR, AutoDoc, ModuleDoc):
"""
def __init__(self, n_TABLES=1, n_LEDs=3):
# On Colorlight-5A-75B/Lattice ECP5-25 (@i7/4th gen.):
# 1x 256 NeoPixels Memory() option yields only 63%
# 2 pins with 256 NeoPixels each yields only 65%
# 4 pins with 256 NeoPixels each yields 94%
# 8 pins à 256 NeoPixels each yields 101% DP16KD -> fail!
# 16 pins simultaneously driven (w/ 256 NeoPixels each) yield 94%
# Inputs
self.b24Data2Load = CSRStorage(24, reset_less=True,
fields=[CSRField("Data2Load", size=24, description="*Field*: 24-Bit value")],
@ -109,7 +107,7 @@ class NeoPixelEngine(Module, AutoCSR, AutoDoc, ModuleDoc):
storage = Memory(24, n_TABLES * n_LEDs)
self.specials += storage
wrport = storage.get_port(write_capable=True) #, clock_domain="write")
wrport = storage.get_port(write_capable=True)
self.specials += wrport
self.comb += [ # Write to memory
wrport.adr.eq((self.b4LoadTable.storage * n_LEDs) + self.b8LoadOffset.storage),
@ -133,18 +131,24 @@ class NeoPixelEngine(Module, AutoCSR, AutoDoc, ModuleDoc):
If((self.bEnable.storage==True) and (self.b8Len.storage > 0),
NextValue(self.b4Table, 0), # Start @ 1st table
NextValue(self.b8Offset, 0), # Start @ 1st 24-bit data (mem will be ready next cycle)
NextState("IDLE")
NextValue(self.b5Count24, 0), # Bit count 0..23
NextState("IDLE1")
)
)
fsm.act("IDLE",
If((self.bEnable.storage==True) and (self.b8Len.storage > 0),
NextValue(self.b24GRB, rdport.dat_r), # Depends upon b4Table/b8Offset
NextValue(self.b5Count24, 0), # Bit count 0..23
NextState("PREPAREBIT")
)
# G/R/B Word loop entry:
fsm.act("IDLE1", # 1st cycle delay for memory port access
NextState("IDLE2")
)
fsm.act("IDLE2", # 2nd cycle delay ...
NextState("IDLE3")
)
fsm.act("IDLE3",
NextValue(self.b24GRB, rdport.dat_r), # Depends upon b4Table/b8Offset
NextValue(self.b5Count24, 0), # Bit count 0..23
NextState("PREPAREBIT")
)
# 24-bit loop entry:
# Protocol: T0H=400ns/T0L=850ns, T1H=800ns/T1L=450ns, RST>50µs(>50000ns)
fsm.act("PREPAREBIT",
If(self.b24GRB[23],
@ -235,7 +239,7 @@ class NeoPixelEngine(Module, AutoCSR, AutoDoc, ModuleDoc):
fsm.act("NEXTTABLE",
If(self.b4Table < 16,
NextValue(self.b8Offset, 0), # Start @ 1st 24-bit data
NextState("IDLE")
NextState("IDLE1")
).Else(
NextState("IDLETABLE")
)

43698
npe.vcd

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