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Neopixelar
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Rewrite-Trial for test board

master
kaqu 2020-11-21 18:39:36 +01:00
parent b8ba9107d9
commit 80fc7babf3
1 changed files with 15 additions and 5 deletions
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20
neopixelar.py
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@ -337,7 +337,16 @@ class BaseSoC(SoCCore):
# OR values for LED signalling test
# For U28
J1_1 = Signal(1) # Pins for logical evaluation
self.J1_1 = J1_1 = platform.request("gpio", 0) # Pins for logical evaluation
self.J1_2 = J1_2 = platform.request("gpio", 1)
self.J1_3 = J1_3 = platform.request("gpio", 2)
self.J1_5 = J1_5 = platform.request("gpio", 3)
self.J1_6 = J1_6 = platform.request("gpio", 4)
self.J1_7 = J1_7 = platform.request("gpio", 5)
self.J2_1 = J2_1 = platform.request("gpio", 14)
self.J2_2 = J2_2 = platform.request("gpio", 15)
'''
J1_1 = Signal(1)
self.comb += J1_1.eq(platform.request("gpio", 0)) # Input data pins
J1_2 = Signal(1)
self.comb += J1_2.eq(platform.request("gpio", 1))
@ -370,11 +379,12 @@ class BaseSoC(SoCCore):
self.comb += J8_6.eq(platform.request("gpio", 102))
J8_7 = Signal(1)
self.comb += J8_7.eq(platform.request("gpio", 103))
'''
# OR it all together
led_logic1 = Signal(1)
self.led_logic1 = led_logic1 = Signal(1)
self.comb += led_logic1.eq(J1_1 | J1_2 | J1_3 | J1_5 | J1_6 | J1_7 | J2_1 | J2_2)
led_logic2 = Signal(1)
self.comb += led_logic2.eq(J8_1 | J8_2 | J8_3 | J8_5 | J8_6 | J8_7 | J7_5 | J7_7)
#led_logic2 = Signal(1)
#self.comb += led_logic2.eq(J8_1 | J8_2 | J8_3 | J8_5 | J8_6 | J8_7 | J7_5 | J7_7)
# Base counter (used for clocking)
counter = Signal(32) # 32-Bit counter
@ -383,7 +393,7 @@ class BaseSoC(SoCCore):
# USERLED blink (on-board LED)
# only w/ uart-name=crossover option:
if kwargs["uart_name"] not in ["serial", "bridge"]:
self.comb += platform.request("user_led_n").eq(counter[23] | led_logic1 | led_logic2) # ~2Hz
self.comb += platform.request("user_led_n").eq(counter[23] | led_logic1) #| led_logic2) # ~2Hz
# Adjust no. for your actual project ...
max_TABLES = 3 # 1..16