Flash to upper region finally working!

master
kaqu 2 years ago
parent 9367a9b6d0
commit 73f226cc66
  1. 1
      .gitignore
  2. 4
      .vscode/launch.json
  3. BIN
      helpers/__pycache__/bit_to_flash.cpython-38.pyc
  4. BIN
      helpers/__pycache__/load_to_flash.cpython-38.pyc
  5. BIN
      helpers/__pycache__/prepare_firmware.cpython-38.pyc
  6. 89
      helpers/eraser.svf
  7. 29
      helpers/imageflasher.py
  8. 21
      helpers/load_to_flash.py
  9. 10
      neopixelar.py
  10. 78
      software/flashcreate.sh
  11. 3
      software/ramcreate.sh

1
.gitignore vendored

@ -2,3 +2,4 @@ build/*
__pycache__/*
backup/*
software/build/*
hd_errors/*

@ -10,8 +10,8 @@
"request": "launch",
"program": "${file}",
"args": ["--build",
//"--load", // May be used separately ...
"--flash", // May be used separately ...
"--load", // May be used separately ...
//"--flash", // May be used separately ...
"--revision=7.0",
"--uart-name=crossover",
//"--with-ethernet", // Not to be used together w/ etherbone! Won't TFTP ...

@ -0,0 +1,89 @@
// **Nur mal so als Versuch**
STATE RESET;
HDR 0;
HIR 0;
TDR 0;
TIR 0;
ENDDR DRPAUSE;
ENDIR IRPAUSE;
STATE IDLE;
SIR 8 TDI (E0);
SDR 32 TDI (00000000)
TDO (41111043)
MASK (FFFFFFFF);
SIR 8 TDI (1C);
SDR 510 TDI (3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF);
// Enter Programming mode
SIR 8 TDI (C6);
SDR 8 TDI (00);
RUNTEST IDLE 2 TCK 1.00E-02 SEC;
// Erase
SIR 8 TDI (0E);
SDR 8 TDI (01);
RUNTEST IDLE 2 TCK 2.0E-1 SEC;
// Read STATUS
SIR 8 TDI (3C);
SDR 32 TDI (00000000)
TDO (00000000)
MASK (0000B000);
// Exit Programming mode
SIR 8 TDI (26);
RUNTEST IDLE 2 TCK 1.00E-02 SEC;
// BYPASS
SIR 8 TDI (FF);
STATE IDLE;
RUNTEST 32 TCK;
RUNTEST 2.00E-2 SEC;
// Enter SPI mode
SIR 8 TDI (3A);
SDR 16 TDI (68FE);
STATE IDLE;
RUNTEST 32 TCK;
RUNTEST 2.00E-2 SEC;
// SPI IO (CMD 0xAB release Power Down???)
SDR 8 TDI (D5);
RUNTEST 2.00E-0 SEC;
// CONFIRM FLASH ID (CMD 0x9f JEDEC Flash Id -> Size must be 0x16)
!SDR 32 TDI (000000F9)
! TDO (68FFFFFF)
! MASK (FF000000);
// CMD 0x06 Write Enable + 0x01 Write 0x00 to Status Register
SDR 8 TDI(60);
SDR 16 TDI(0080);
RUNTEST 1.00E-0 SEC;
// **CMD 0x06 Write Enable + 0xc7 Chip Erase**
SDR 8 TDI (60);
SDR 8 TDI (e3);
// Warten bis Fertig ... vieleicht reichen 3 Minuten
RUNTEST 180.00 SEC;
// BYPASS
SIR 8 TDI (FF);
//REFRESH
SIR 8 TDI(79);
SDR 24 TDI(000000);
STATE IDLE;
RUNTEST 32 TCK;
RUNTEST 2.00E-2 SEC;
STATE RESET;

@ -1,10 +1,11 @@
#!/usr/bin/env python3
#
# bit_to_uploadflash.py
# Very basic bitstream to SVF converter, tested with the ULX3S WiFi interface
#
# Modified a little to be used as integral module ...
# imageflasher.py
#
# History:
# --------
# 23.10.20/KQ Working version ...
#
import os
@ -21,7 +22,7 @@ def bitreverse(x):
y |= (1 << i)
return y
def convertBitToUploadFlashFile(bitFile, FlashFile, flash_page_size = 256, address = 0, erase_block_size = 64*1024):
def convertBitToUploadFlashFile(bitFile, FlashFile, flash_page_size = 256, address = 0, erase_block_size = 64*1024, id_provided = 0):
with open(bitFile, 'rb') as bitf:
bs = bitf.read()
# Autodetect IDCODE from bitstream
@ -34,10 +35,14 @@ def convertBitToUploadFlashFile(bitFile, FlashFile, flash_page_size = 256, addre
idcode |= bs[i+6] << 8
idcode |= bs[i+7]
break
if id_provided != 0:
print("ID provided externally!")
idcode = id_provided
if idcode is None:
print("Failed to find IDCODE in bitstream, check bitstream is valid")
sys.exit(1)
print("IDCODE in bitstream is 0x%08x" % idcode)
bitf.seek(0)
last_page = -1
@ -170,12 +175,8 @@ if __name__ == "__main__":
relpath = "../"
else:
relpath = "./"
#filename = os.getcwd() + relpath + "/software/build/main"
filename = relpath + "build/colorlight_5a_75b/gateware/colorlight_5a_75b"
os.chdir(relpath + "build/colorlight_5a_75b/gateware")
os.system(f"ecppack colorlight_5a_75b.config --svf colorlight_5a_75b.svf --bit colorlight_5a_75b.bit --bootaddr 0xC0100000")
os.chdir(pwd)
print(f"Translating {filename}.bit to {filename}.svf.flash")
convertBitToUploadFlashFile(filename + ".bit", filename + ".svf.flash", address=0x100000)
print(f"Load/flash {filename}.svf.flash ...")
load2flash(filename + ".svf.flash")
filename = relpath + "software/build/main" # Fixed main.img!
print(f"Translating {filename}.img to {filename}.svf")
convertBitToUploadFlashFile(filename + ".img", filename + ".svf", address=0x100000, id_provided= 0x41111043)
print(f"Load/flash {filename}.svf ...")
load2flash(filename + ".svf")

@ -20,13 +20,24 @@ jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043
f.close()
os.system(f"openocd -f prog/openocd.cfg -c \"transport select jtag; init; svf {file}; exit\"")
def eraseflash(file):
load2flash(file)
if __name__ == "__main__":
_, tail = os.path.split(os.getcwd())
bLoadProgram = False # False = Erase instead!
pwd = os.getcwd()
_, tail = os.path.split(pwd)
if tail == "helpers": # Started within subdir?
relpath = ".."
else:
relpath = "."
filename = relpath + "/build/colorlight_5a_75b/gateware/colorlight_5a_75b"
print(f"Load/flash {filename}.svf.flash ...")
load2flash(filename + ".svf.flash")
print("Done.")
if bLoadProgram == True:
filename = relpath + "/build/colorlight_5a_75b/gateware/colorlight_5a_75b"
print(f"Load/flash {filename}.svf.flash ...")
load2flash(filename + ".svf.flash")
print("Done.")
else:
filename = relpath + "/helpers/eraser.svf"
print("Erasing flash w/ {0}(expect 5 min. waiting time ...)".format(filename))
eraseflash(filename)
print("Done.")

@ -388,14 +388,16 @@ def main():
**soc_core_argdict(args))
# 32MBit SPIFlash (not used currently) ---------------------------------------------------------------
soc.mem_map["spiflash"] = 0xc0000000 # Length: 0x01000000 ('til 0xc1000000 - 1)
flashbase = 0xc0000000
flashoffset = 0x100000 # Used to be zero (default)
soc.mem_map["spiflash"] = flashbase # Length: 0x01000000 ('til 0xc1000000 - 1)
# Boot at +1MB
soc.add_constant("FLASH_BOOT_ADDRESS", soc.mem_map["spiflash"] + 1024*1024) # 0xc0100000
soc.add_spi_flash(name="spiflash", mode="1x", dummy_cycles=8, clk_freq=5e6)
builder = Builder(soc, **builder_argdict(args))
# Now override boot address
args.ecppack_bootaddr = 0xC0100000
# Now override boot address (used to be zero/default)
args.ecppack_bootaddr = flashbase + flashoffset # 0xC0100000
builder.build(**trellis_argdict(args), run=args.build) # Written here to (local) build tree
if args.doc:
@ -412,7 +414,7 @@ def main():
name = os.path.join(builder.gateware_dir, soc.build_name)
print(f"Executing ./bit_to_flash.py {name}.bit {name}.svf.flash")
from helpers.bit_to_flash import convertBitToFlashFile
convertBitToFlashFile(name + ".bit", name + ".svf.flash")
convertBitToFlashFile(name + ".bit", name + ".svf.flash", address=flashoffset)
from helpers.load_to_flash import load2flash
load2flash(name + ".svf.flash")
return

@ -5,77 +5,11 @@
#
# History:
# --------
# 21.10.20/KQ Initial (running) version
# 21.10.20/KQ Initial version
# 23.10.20/KQ Worx great now!
#
# Test for missing ('zero length') basefilenames
if [ -z $1 ] || [ -z $2 ]; then
echo "usage: ./flashcreate.sh <mainfile_w/o_extension> <jobfile_w/o_extension>"
exit
fi
# Adjust these paths according to your local installation !!!
MY_LOCAL_LITEX_PATH=$HOME"/fpga/litex"
MY_LOCAL_FOMU_PATH=$HOME"/Fomu"
# If you don't use a virtual environment, comment out next line ...
source $HOME/fpga/bin/activate
# Make sure, we use the right compiler version ...
export PATH=$PATH:$MY_LOCAL_LITEX_PATH/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin/
TRIPLE="riscv64-unknown-elf"
CPU="vexriscv"
CPUFLAGS="-march=rv32i -mabi=ilp32 -D__vexriscv__"
CPUENDIANNESS="little"
CPU_DIRECTORY="$MY_LOCAL_LITEX_PATH/litex/litex/soc/cores/cpu/vexriscv"
COMPILER_RT_DIRECTORY="$MY_LOCAL_LITEX_PATH/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data"
SOC_DIRECTORY="$MY_LOCAL_LITEX_PATH/litex/litex/soc"
#export BUILDINC_DIRECTORY
BUILDINC_DIRECTORY="/mnt/a30054ad-3fe6-444a-8d93-16df937e448e/projects/fpga/neopixelar/build/colorlight_5a_75b/software/include"
LIBCOMPILER_RT_DIRECTORY="$MY_LOCAL_LITEX_PATH/litex/litex/soc/software/libcompiler_rt"
LIBBASE_DIRECTORY="$MY_LOCAL_LITEX_PATH/litex/litex/soc/software/libbase"
LIBLITEDRAM_DIRECTORY="$MY_LOCAL_LITEX_PATH/litex/litex/soc/software/liblitedram"
LIBLITEETH_DIRECTORY="$MY_LOCAL_LITEX_PATH/litex/litex/soc/software/libliteeth"
LIBLITESPI_DIRECTORY="$MY_LOCAL_LITEX_PATH/litex/litex/soc/software/liblitespi"
LIBLITESDCARD_DIRECTORY="$MY_LOCAL_LITEX_PATH/litex/litex/soc/software/liblitesdcard"
BIOS_DIRECTORY="$MY_LOCAL_LITEX_PATH/litex/litex/soc/software/bios"
BIOSPATH="/mnt/a30054ad-3fe6-444a-8d93-16df937e448e/projects/fpga/neopixelar/build/colorlight_5a_75b/software/bios"
OBJECTS="$BIOSPATH/isr.o $BIOSPATH/boot-helper.o $BIOSPATH/boot.o $BIOSPATH/helpers.o $BIOSPATH/cmd_bios.o $BIOSPATH/cmd_mem.o $BIOSPATH/cmd_boot.o $BIOSPATH/cmd_i2c.o $BIOSPATH/cmd_spiflash.o $BIOSPATH/cmd_litedram.o $BIOSPATH/cmd_liteeth.o $BIOSPATH/cmd_litesdcard.o $BIOSPATH/complete.o $BIOSPATH/readline.o"
LXP="../build/colorlight_5a_75b/software"
CRT0="$LXP/libbase/crt0.o"
LXR="-L$LXP/libcompiler_rt -L$LXP/libbase -L$LXP/liblitedram -L$LXP/libliteeth -L$LXP/liblitespi -L$LXP/liblitesdcard -llitedram -lliteeth -llitespi -llitesdcard -lbase-nofloat -lcompiler_rt"
INCLUDES="-I$SOC_DIRECTORY/software/include/base -I$SOC_DIRECTORY/software/include -I$SOC_DIRECTORY/software -I$BUILDINC_DIRECTORY -I$CPU_DIRECTORY -I$BIOS_DIRECTORY"
# -Os optimize for size
#COMMONFLAGS="-Os $CPUFLAGS -g3 -fomit-frame-pointer -Wall -fno-builtin -nostdinc $INCLUDES"
COMMONFLAGS="-O0 $CPUFLAGS -g3 -fomit-frame-pointer -Wall -fno-builtin -nostdinc $INCLUDES"
CFLAGS="-fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes"
LDFLAGS="-nostdlib -nodefaultlibs -L$BUILDINC_DIRECTORY"
echo "--"
echo "calling gcc with: -c $COMMONFLAGS $CFLAGS -Wa,-fPIC for $1 & $2"
#$MY_LOCAL_LITEX_PATH/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc -O0 -S -nostdinc $COMMONFLAGS $INCLUDES -Wa,-fPIC source/$1.c
$MY_LOCAL_LITEX_PATH/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc -c $COMMONFLAGS $CFLAGS -Wa,-fPIC source/$2.c -o build/$2.o
$MY_LOCAL_LITEX_PATH/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc -c $COMMONFLAGS $CFLAGS -Wa,-fPIC source/$1.c -o build/$1.o
echo "--"
echo "calling ld for flash with: $LDFLAGS $OBJECTS build/$2.o build/$1.o -o build/$1.bin"
$MY_LOCAL_LITEX_PATH/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-ld $LDFLAGS -T linker/flash.ld -N $CRT0 $OBJECTS $LXR build/$2.o build/$1.o -o build/$1.elf
echo "--"
echo "creating raw binary from elf-file"
$MY_LOCAL_LITEX_PATH/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/riscv64-unknown-elf/bin/objcopy -O binary -S --image-base 0xc0100000 build/$1.elf build/$1.bin
#echo "--"
#echo "creating disassembly dump build/$1.dis"
#$MY_LOCAL_LITEX_PATH/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-objdump -D -b binary build/$1.bin -m riscv >build/$1.dis
ecppack colorlight_5a_75b.config --svf colorlight_5a_75b.svf --bit colorlight_5a_75b.bit --bootaddr 0xc0100000
#echo "--"
#echo "loading build/$1.bin to flash boot adress via wishbone-tool"
#$MY_LOCAL_FOMU_PATH/fomu-toolchain-linux_x86_64-v1.5.6/bin/wishbone-tool --ethernet-host 192.168.1.20 --server load-file --csr-csv ../build/csr.csv --load-address 0xc0100000 --load-name build/$1.bin
#echo "--"
#echo "Connecting to remote terminal w/ wishbone-tool (press ESC to terminate ...)"
#$MY_LOCAL_FOMU_PATH/fomu-toolchain-linux_x86_64-v1.5.6/bin/wishbone-tool --ethernet-host 192.168.1.20 --server terminal --csr-csv ../build/csr.csv
# alternatively use:
# screen /dev/ttyUSB0 115200
# Press 'Ctrl-A k' to terminate ...
echo "Done (don't worry about the download 'error' in red!)."
echo "Flashing image ..."
cd ..
python3 helpers/imageflasher.py
cd software

@ -76,6 +76,9 @@ fi
#echo "creating disassembly dump build/$1.dis"
#$MY_LOCAL_LITEX_PATH/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-objdump -D -b binary build/$1.bin -m riscv >build/$1.dis
echo "--"
echo "Creating flashable image"
python3 -m litex.soc.software.mkmscimg build/$1.bin --little --fbi --output build/$1.img
echo "--"
echo "loading build/$1.bin to RAM base via wishbone-tool"
if [ "$3" = "1" ]; then
echo "for bank #1"

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