Neopixelar - the FPGA project
This project demonstrates the use of LiteX & migen to create a Neopixel driving FPGA based h/w unit,
called NPE (‘neopixel engine’). The project requires a colorlight-5a-75b board (sells at ~18€ as of 10/2020). A RISC-V CPU (RV32I) is incorporated as well as network RAM loading (2 banks!) & separate application flashing capability (MUCH faster, bringing flashboot
(Hint: project has been tested on Linux Mint 20 only, but should run on other Linux versions as well ...)
To use this project effectively, you will have to install LiteX, see https://github.com/enjoy-digital/litex for details (and project Trellis, NextPNR & YoSys requirements).
Also, it is recommended to install the board support, see https://github.com/litex-hub/litex-boards,
as well as the the RISC-V tool chain (see https://github.com/sifive/freedom-tools/releases).
To communicate with your board via network, install the wishbone tools, see https://github.com/litex-hub/wishbone-utils.
To use the automatic documentation feature, you will have to install sphinx, see https://www.sphinx-doc.org/en/master. Also its wavedrom extension has to be installed, see https://pypi.org/project/wavedrom.
Some helpful links for RST docstring formats:
The project assumes a local ‘fpga’ path within the home directory of the user, where all the above mentioned software packages are installed.
Furthermore, the project assumes a virtual environment named ‘fpga’ where all project relevant python libs are registered (this is not strictly necessary ... maybe software/ramcreate.sh has to be adjusted, as well as the python interpreter settings within VSC!).
The actual ‘Neopixelar’ project may be installed anywhere, but local paths will have to be adjusted (firmware/main.c, software/ramcreate.sh ... worx for me ;).
A JTAG programmer will be required for successful device programming. Thanx to Wolfgang, I’m using the Versaloon (s/w for blue-pill STM32), see https://github.com/zoobab/versaloon. To use this device, you also will have to install openocd via ‘apt install openocd’. See https://git.hacknology.de/wolfgang/colorlight#user-content-class-hub75sender for details, on how to connect the JTAG adapter.
For board specific details see
Other helpful links to board data:
- Neopixelar.py - this is the main FPGA building source
- neopixelengine.py - this is the actual NeoPixel driving engine
- helpers subdir - contains python helpers for load & flash etc.
- firmware subdir - contains some modified BIOS files (relative to the original version)
- software subdir - contains a separate build, load & flash logic for separate (RV32i) application code
(the rest is of minor importance ...)
After installation of the relevant toolchains:
- Open the project in VSC (or use your favourite IDE & maybe adjust some settings ;), adjust local paths if nec. ...
- Connect your JTAG adapter as described in Wolfgang’s documentation @ https://git.hacknology.de/wolfgang/colorlight
- Run neopixelar.py with these options (you may omit the --doc option if there is no Sphinx installed):
--build --load --revision=7.0 --uart-name=crossover --with-etherbone --ip-address=192.168.1.20 --csr-csv=build/csr.csv --doc
to create & load the project to on-board SRAM via the USB/JTAG-Adapter (this takes it’s time ...)
- Connect a Neopixel LED chain to J4/Pin 1 (the logic supports 16 pins w/ 256 LEDs per chain, the demo features 3 pins w/ 27 LEDs each)
- Press reset on the board, the LED chain should become illuminated
- To program this base logic permanently, the board has to be improved, add a capacitor to stabilize the voltage for FPGA
programming (see Wolfgang’s documentation on https://git.hacknology.de/wolfgang/colorlight )
- Now run the same sequence as mentioned above, this time replacing the --load option with the --flash option
- This time it will take even longer ...
- And hopefully complete without errors. If successful, the basic ROM s/w is now in place & operating. In case of errors try again - rule out EMI disturbances if nec.
- Create the actual documentation for html via: ‘sphinx-build -b html build/documentation build/documentation/html’
- Use your favourite browser to access the ‘npe’ units documentation via ‘file://your_projectpath/build/documentation build/documentation/html/index.html’
Individual (separate) applications
- This time, open up a terminal & cd to the project local ‘software’ subdirectory
- You can load an application to RAM bank 1:
./ramcreate.sh main illumination 1
- To run the (now) RAM based application, type ‘cd ..’ within terminal
- Connect the Litex-Terminal to the board via:
wishbone-tool --ethernet-host 192.168.1.20 --server terminal --csr-csv build/csr.csv
- Type ‘ramboot’ into terminal, the RAM based application should come up now
- Press ‘s’ (Speedup) to speed up the lights, ‘w’ (sloWdown) to slow them down
- Press ‘x’ (eXit) to abort the application, you should see the LiteX prompt now
- You can load an application to RAM bank 2:
./ramcreate.sh main illumination 2
- Now, use ‘ramboot’ again! The system should swap to RAM bank #2 and boot the application right away
- This is the testing loop, once your happy w/ your application, it needs to be flashed
- !CAREFULL NOW! The application shouldn’t contain any errors as it will be booted right after the BIOS
- Make sure, your JTAG adapter is in place!
- This flashes the application permanently to the boot address, where it will be verified by the BIOS
and started automatically (the good news: the 64kBytes of the sample application only take some 18 s ...)
- You probably want to modify the application now ... (for development purposes, I recommend the quicker RAM bank
loading - to get rid of an annoying flashed app, you may also use ./flashclearapp.sh ;)